Commit 08ab88f5 authored by Ben Skeggs's avatar Ben Skeggs Committed by Dave Airlie
Browse files

drm/nouveau/nvenc/r535: initial support 



Adds support for allocating VIDEO_ENCODER classes from RM.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230918202149.4343-43-skeggsb@gmail.com
parent 142cd602

drivers/gpu/drm/nouveau/include/nvif/class.h

+4 −0
Original line number Diff line number Diff line
@@ -231,6 +231,10 @@ 
#define AMPERE_DMA_COPY_A                                            0x0000c6b5

#define AMPERE_DMA_COPY_B                                            0x0000c7b5



#define NVC4B7_VIDEO_ENCODER                                         0x0000c4b7

#define NVC7B7_VIDEO_ENCODER                                         0x0000c7b7

#define NVC9B7_VIDEO_ENCODER                                         0x0000c9b7



#define FERMI_DECOMPRESS                                             0x000090b8



#define NV50_COMPUTE                                                 0x000050c0

drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h

+2 −0
Original line number Diff line number Diff line
@@ -13,4 +13,6 @@ struct nvkm_nvenc { 


int gm107_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **);

int tu102_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **);

int ga102_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **);

int ad102_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **);

#endif

drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/nvos.h

+7 −0
Original line number Diff line number Diff line
@@ -112,6 +112,13 @@ typedef struct 
    NvU32 engineInstance;               // Select NVDEC0 or NVDEC1 or NVDEC2

} NV_BSP_ALLOCATION_PARAMETERS;



typedef struct

{

    NvU32 size;

    NvU32 prohibitMultipleInstances;  // Prohibit multiple allocations of MSENC?

    NvU32 engineInstance;             // Select MSENC/NVENC0 or NVENC1 or NVENC2

} NV_MSENC_ALLOCATION_PARAMETERS;



typedef struct

{

    NvU32   index;

drivers/gpu/drm/nouveau/include/nvrm/535.54.03/nvidia/inc/kernel/gpu/intr/engine_idx.h

+4 −0
Original line number Diff line number Diff line
@@ -32,6 +32,10 @@ 


#define MC_ENGINE_IDX_CE9                           24



#define MC_ENGINE_IDX_MSENC                         38



#define MC_ENGINE_IDX_MSENC2                        40



#define MC_ENGINE_IDX_GSP                           49



#define MC_ENGINE_IDX_BSP                           64

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

+10 −0
Original line number Diff line number Diff line
@@ -2622,6 +2622,7 @@ nv172_chipset = { 
	.fifo     = { 0x00000001, ga102_fifo_new },

	.gr       = { 0x00000001, ga102_gr_new },

	.nvdec    = { 0x00000003, ga102_nvdec_new },

	.nvenc    = { 0x00000001, ga102_nvenc_new },

	.sec2     = { 0x00000001, ga102_sec2_new },

};
@@ -2652,6 +2653,7 @@ nv173_chipset = { 
	.fifo     = { 0x00000001, ga102_fifo_new },

	.gr       = { 0x00000001, ga102_gr_new },

	.nvdec    = { 0x00000003, ga102_nvdec_new },

	.nvenc    = { 0x00000001, ga102_nvenc_new },

	.sec2     = { 0x00000001, ga102_sec2_new },

};
@@ -2682,6 +2684,7 @@ nv174_chipset = { 
	.fifo     = { 0x00000001, ga102_fifo_new },

	.gr       = { 0x00000001, ga102_gr_new },

	.nvdec    = { 0x00000003, ga102_nvdec_new },

	.nvenc    = { 0x00000001, ga102_nvenc_new },

	.sec2     = { 0x00000001, ga102_sec2_new },

};
@@ -2712,6 +2715,7 @@ nv176_chipset = { 
	.fifo     = { 0x00000001, ga102_fifo_new },

	.gr       = { 0x00000001, ga102_gr_new },

	.nvdec    = { 0x00000003, ga102_nvdec_new },

	.nvenc    = { 0x00000001, ga102_nvenc_new },

	.sec2     = { 0x00000001, ga102_sec2_new },

};
@@ -2742,6 +2746,7 @@ nv177_chipset = { 
	.fifo     = { 0x00000001, ga102_fifo_new },

	.gr       = { 0x00000001, ga102_gr_new },

	.nvdec    = { 0x00000003, ga102_nvdec_new },

	.nvenc    = { 0x00000001, ga102_nvenc_new },

	.sec2     = { 0x00000001, ga102_sec2_new },

};
@@ -2765,6 +2770,7 @@ nv192_chipset = { 
	.fifo     = { 0x00000001, ga102_fifo_new },

	.gr       = { 0x00000001, ad102_gr_new },

	.nvdec    = { 0x0000000f, ad102_nvdec_new },

	.nvenc    = { 0x00000007, ad102_nvenc_new },

	.sec2     = { 0x00000001, ga102_sec2_new },

};
@@ -2788,6 +2794,7 @@ nv193_chipset = { 
	.fifo     = { 0x00000001, ga102_fifo_new },

	.gr       = { 0x00000001, ad102_gr_new },

	.nvdec    = { 0x0000000f, ad102_nvdec_new },

	.nvenc    = { 0x00000007, ad102_nvenc_new },

	.sec2     = { 0x00000001, ga102_sec2_new },

};
@@ -2811,6 +2818,7 @@ nv194_chipset = { 
	.fifo     = { 0x00000001, ga102_fifo_new },

	.gr       = { 0x00000001, ad102_gr_new },

	.nvdec    = { 0x0000000f, ad102_nvdec_new },

	.nvenc    = { 0x00000007, ad102_nvenc_new },

	.sec2     = { 0x00000001, ga102_sec2_new },

};
@@ -2834,6 +2842,7 @@ nv196_chipset = { 
	.fifo     = { 0x00000001, ga102_fifo_new },

	.gr       = { 0x00000001, ad102_gr_new },

	.nvdec    = { 0x0000000f, ad102_nvdec_new },

	.nvenc    = { 0x00000007, ad102_nvenc_new },

	.sec2     = { 0x00000001, ga102_sec2_new },

};
@@ -2857,6 +2866,7 @@ nv197_chipset = { 
	.fifo     = { 0x00000001, ga102_fifo_new },

	.gr       = { 0x00000001, ad102_gr_new },

	.nvdec    = { 0x0000000f, ad102_nvdec_new },

	.nvenc    = { 0x00000007, ad102_nvenc_new },

	.sec2     = { 0x00000001, ga102_sec2_new },

};