Commit 096f286e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS updates from Thomas Bogendoerfer:
 "Just cleanups and fixes"

* tag 'mips_6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  MIPS: Alchemy: Fix an out-of-bound access in db1550_dev_setup()
  MIPS: Alchemy: Fix an out-of-bound access in db1200_dev_setup()
  MIPS: Fix typos
  MIPS: Remove unused shadow GPR support from vector irq setup
  MIPS: Allow vectored interrupt handler to reside everywhere for 64bit
  mips: Set dump-stack arch description
  mips: mm: add slab availability checking in ioremap_prot
  mips: Optimize max_mapnr init procedure
  mips: Fix max_mapnr being uninitialized on early stages
  mips: Fix incorrect max_low_pfn adjustment
  mips: dmi: Fix early remap on MIPS32
  MIPS: compressed: Use correct instruction for 64 bit code
  MIPS: SGI-IP27: hubio: fix nasid kernel-doc warning
  MAINTAINERS: Add myself as maintainer of the Ralink architecture
parents 4331f070 3c1e5abc

MAINTAINERS

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@@ -18196,6 +18196,7 @@ F: drivers/media/cec/usb/rainshadow/ 








RALINK MIPS ARCHITECTURE









M:	John Crispin <john@phrozen.org>









M:	Sergio Paracuellos <sergio.paracuellos@gmail.com>









L:	linux-mips@vger.kernel.org









S:	Maintained









F:	arch/mips/ralink

























arch/mips/alchemy/devboards/db1200.c



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@@ -847,7 +847,7 @@ int __init db1200_dev_setup(void)







	i2c_register_board_info(0, db1200_i2c_devs,









				ARRAY_SIZE(db1200_i2c_devs));









	spi_register_board_info(db1200_spi_devs,









				ARRAY_SIZE(db1200_i2c_devs));









				ARRAY_SIZE(db1200_spi_devs));



















	/* SWITCHES:	S6.8 I2C/SPI selector  (OFF=I2C	 ON=SPI)









	 *		S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
































arch/mips/alchemy/devboards/db1550.c



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@@ -589,7 +589,7 @@ int __init db1550_dev_setup(void)







	i2c_register_board_info(0, db1550_i2c_devs,









				ARRAY_SIZE(db1550_i2c_devs));









	spi_register_board_info(db1550_spi_devs,









				ARRAY_SIZE(db1550_i2c_devs));









				ARRAY_SIZE(db1550_spi_devs));



















	c = clk_get(NULL, "psc0_intclk");









	if (!IS_ERR(c)) {
































arch/mips/bcm47xx/buttons.c



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@@ -147,21 +147,21 @@ static const struct gpio_keys_button







bcm47xx_buttons_buffalo_whr_g125[] __initconst = {









	BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),









	BCM47XX_GPIO_KEY(4, KEY_RESTART),









	BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */









	BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode switch */









};



















static const struct gpio_keys_button









bcm47xx_buttons_buffalo_whr_g54s[] __initconst = {









	BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),









	BCM47XX_GPIO_KEY_H(4, KEY_RESTART),









	BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */









	BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode switch */









};



















static const struct gpio_keys_button









bcm47xx_buttons_buffalo_whr_hp_g54[] __initconst = {









	BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),









	BCM47XX_GPIO_KEY(4, KEY_RESTART),









	BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */









	BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode switch */









};



















static const struct gpio_keys_button
































arch/mips/bcm63xx/clk.c



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@@ -174,7 +174,7 @@ static void enetsw_set(struct clk *clk, int enable)







	}



















	if (enable) {









		/* reset switch core afer clock change */









		/* reset switch core after clock change */









		bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1);









		msleep(10);









		bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 0);








@@ -304,7 +304,7 @@ static void xtm_set(struct clk *clk, int enable)







	bcm_hwclock_set(CKCTL_6368_SAR_EN, enable);



















	if (enable) {









		/* reset sar core afer clock change */









		/* reset sar core after clock change */









		bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 1);









		mdelay(1);









		bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 0);