Commit 4331f070 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-6.8-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V updates from Palmer Dabbelt:

 - Support for many new extensions in hwprobe, along with a handful of
   cleanups

 - Various cleanups to our page table handling code, so we alwayse use
   {READ,WRITE}_ONCE

 - Support for the which-cpus flavor of hwprobe

 - Support for XIP kernels has been resurrected

* tag 'riscv-for-linus-6.8-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (52 commits)
  riscv: hwprobe: export Zicond extension
  riscv: hwprobe: export Zacas ISA extension
  riscv: add ISA extension parsing for Zacas
  dt-bindings: riscv: add Zacas ISA extension description
  riscv: hwprobe: export Ztso ISA extension
  riscv: add ISA extension parsing for Ztso
  use linux/export.h rather than asm-generic/export.h
  riscv: Remove SHADOW_OVERFLOW_STACK_SIZE macro
  riscv; fix __user annotation in save_v_state()
  riscv: fix __user annotation in traps_misaligned.c
  riscv: Select ARCH_WANTS_NO_INSTR
  riscv: Remove obsolete rv32_defconfig file
  riscv: Allow disabling of BUILTIN_DTB for XIP
  riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macro
  riscv: Make XIP bootable again
  riscv: Fix set_direct_map_default_noflush() to reset _PAGE_EXEC
  riscv: Fix module_alloc() that did not reset the linear mapping permissions
  riscv: Fix wrong usage of lm_alias() when splitting a huge linear mapping
  riscv: Check if the code to patch lies in the exit section
  riscv: Use the same CPU operations for all CPUs
  ...
parents 6cff79f4 cb51bfee
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+115 −7
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ is defined in <asm/hwprobe.h>::
    };

    long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count,
                           size_t cpu_count, cpu_set_t *cpus,
                           size_t cpusetsize, cpu_set_t *cpus,
                           unsigned int flags);

The arguments are split into three groups: an array of key-value pairs, a CPU
@@ -20,12 +20,26 @@ set, and some flags. The key-value pairs are supplied with a count. Userspace
must prepopulate the key field for each element, and the kernel will fill in the
value if the key is recognized. If a key is unknown to the kernel, its key field
will be cleared to -1, and its value set to 0. The CPU set is defined by
CPU_SET(3). For value-like keys (eg. vendor/arch/impl), the returned value will
be only be valid if all CPUs in the given set have the same value. Otherwise -1
will be returned. For boolean-like keys, the value returned will be a logical
AND of the values for the specified CPUs. Usermode can supply NULL for cpus and
0 for cpu_count as a shortcut for all online CPUs. There are currently no flags,
this value must be zero for future compatibility.
CPU_SET(3) with size ``cpusetsize`` bytes. For value-like keys (eg. vendor,
arch, impl), the returned value will only be valid if all CPUs in the given set
have the same value. Otherwise -1 will be returned. For boolean-like keys, the
value returned will be a logical AND of the values for the specified CPUs.
Usermode can supply NULL for ``cpus`` and 0 for ``cpusetsize`` as a shortcut for
all online CPUs. The currently supported flags are:

* :c:macro:`RISCV_HWPROBE_WHICH_CPUS`: This flag basically reverses the behavior
  of sys_riscv_hwprobe().  Instead of populating the values of keys for a given
  set of CPUs, the values of each key are given and the set of CPUs is reduced
  by sys_riscv_hwprobe() to only those which match each of the key-value pairs.
  How matching is done depends on the key type.  For value-like keys, matching
  means to be the exact same as the value.  For boolean-like keys, matching
  means the result of a logical AND of the pair's value with the CPU's value is
  exactly the same as the pair's value.  Additionally, when ``cpus`` is an empty
  set, then it is initialized to all online CPUs which fit within it, i.e. the
  CPU set returned is the reduction of all the online CPUs which can be
  represented with a CPU set of size ``cpusetsize``.

All other flags are reserved for future compatibility and must be zero.

On success 0 is returned, on failure a negative error code is returned.

@@ -80,6 +94,100 @@ The following keys are defined:
  * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as
       ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.

  * :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined
       in version 1.0 of the Bit-Manipulation ISA extensions.

  * :c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as
       defined in version 1.0 of the Scalar Crypto ISA extensions.

  * :c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as
       defined in version 1.0 of the Scalar Crypto ISA extensions.

  * :c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as
       defined in version 1.0 of the Scalar Crypto ISA extensions.

  * :c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as
       defined in version 1.0 of the Scalar Crypto ISA extensions.

  * :c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as
       defined in version 1.0 of the Scalar Crypto ISA extensions.

  * :c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as
       defined in version 1.0 of the Scalar Crypto ISA extensions.

  * :c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as
       defined in version 1.0 of the Scalar Crypto ISA extensions.

  * :c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as
       defined in version 1.0 of the Scalar Crypto ISA extensions.

  * :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined
       in version 1.0 of the Scalar Crypto ISA extensions.

  * :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as
       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  * :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as
       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  * :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as
       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  * :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as
       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  * :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as
       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as
       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as
       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  * :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as
       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  * :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as
       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as
       defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.

  * :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported
       as defined in the RISC-V ISA manual.

  * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is
       supported as defined in the RISC-V ISA manual.

  * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0
       is supported as defined in the RISC-V ISA manual.

  * :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as
       defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
       ("Remove draft warnings from Zvfh[min]").

  * :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported as
       defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
       ("Remove draft warnings from Zvfh[min]").

  * :c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported as
       defined in the RISC-V ISA manual starting from commit 056b6ff467c7
       ("Zfa is ratified").

  * :c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as
       defined in the RISC-V ISA manual starting from commit 5618fb5a216b
       ("Ztso is now ratified.")

  * :c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as
       defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
       from commit 5059e0ca641c ("update to ratified").

  * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as
       defined in the RISC-V Integer Conditional (Zicond) operations extension
       manual starting from commit 95cf1f9 ("Add changes requested by Ved
       during signoff")

* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
  information about the selected set of processors.

+1 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ properties:
    oneOf:
      - items:
          - enum:
              - amd,mbv32
              - andestech,ax45mp
              - canaan,k210
              - sifive,bullet0
+219 −0
Original line number Diff line number Diff line
@@ -171,6 +171,12 @@ properties:
            memory types as ratified in the 20191213 version of the privileged
            ISA specification.

        - const: zacas
          description: |
            The Zacas extension for Atomic Compare-and-Swap (CAS) instructions
            is supported as ratified at commit 5059e0ca641c ("update to
            ratified") of the riscv-zacas.

        - const: zba
          description: |
            The standard Zba bit-manipulation extension for address generation
@@ -190,12 +196,111 @@ properties:
            multiplication as ratified at commit 6d33919 ("Merge pull request
            #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.

        - const: zbkb
          description:
            The standard Zbkb bitmanip instructions for cryptography as ratified
            in version 1.0 of RISC-V Cryptography Extensions Volume I
            specification.

        - const: zbkc
          description:
            The standard Zbkc carry-less multiply instructions as ratified
            in version 1.0 of RISC-V Cryptography Extensions Volume I
            specification.

        - const: zbkx
          description:
            The standard Zbkx crossbar permutation instructions as ratified
            in version 1.0 of RISC-V Cryptography Extensions Volume I
            specification.

        - const: zbs
          description: |
            The standard Zbs bit-manipulation extension for single-bit
            instructions as ratified at commit 6d33919 ("Merge pull request #158
            from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.

        - const: zfa
          description:
            The standard Zfa extension for additional floating point
            instructions, as ratified in commit 056b6ff ("Zfa is ratified") of
            riscv-isa-manual.

        - const: zfh
          description:
            The standard Zfh extension for 16-bit half-precision binary
            floating-point instructions, as ratified in commit 64074bc ("Update
            version numbers for Zfh/Zfinx") of riscv-isa-manual.

        - const: zfhmin
          description:
            The standard Zfhmin extension which provides minimal support for
            16-bit half-precision binary floating-point instructions, as ratified
            in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
            riscv-isa-manual.

        - const: zk
          description:
            The standard Zk Standard Scalar cryptography extension as ratified
            in version 1.0 of RISC-V Cryptography Extensions Volume I
            specification.

        - const: zkn
          description:
            The standard Zkn NIST algorithm suite extensions as ratified in
            version 1.0 of RISC-V Cryptography Extensions Volume I
            specification.

        - const: zknd
          description: |
            The standard Zknd for NIST suite: AES decryption instructions as
            ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
            specification.

        - const: zkne
          description: |
            The standard Zkne for NIST suite: AES encryption instructions as
            ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
            specification.

        - const: zknh
          description: |
            The standard Zknh for NIST suite: hash function instructions as
            ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
            specification.

        - const: zkr
          description:
            The standard Zkr entropy source extension as ratified in version
            1.0 of RISC-V Cryptography Extensions Volume I specification.
            This string being present means that the CSR associated to this
            extension is accessible at the privilege level to which that
            device-tree has been provided.

        - const: zks
          description:
            The standard Zks ShangMi algorithm suite extensions as ratified in
            version 1.0 of RISC-V Cryptography Extensions Volume I
            specification.

        - const: zksed
          description: |
            The standard Zksed for ShangMi suite: SM4 block cipher instructions
            as ratified in version 1.0 of RISC-V Cryptography Extensions
            Volume I specification.

        - const: zksh
          description: |
            The standard Zksh for ShangMi suite: SM3 hash function instructions
            as ratified in version 1.0 of RISC-V Cryptography Extensions
            Volume I specification.

        - const: zkt
          description:
            The standard Zkt for data independent execution latency as ratified
            in version 1.0 of RISC-V Cryptography Extensions Volume I
            specification.

        - const: zicbom
          description:
            The standard Zicbom extension for base cache management operations as
@@ -246,6 +351,12 @@ properties:
            The standard Zihintpause extension for pause hints, as ratified in
            commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.

        - const: zihintntl
          description:
            The standard Zihintntl extension for non-temporal locality hints, as
            ratified in commit 0dc91f5 ("Zihintntl is ratified") of the
            riscv-isa-manual.

        - const: zihpm
          description:
            The standard Zihpm extension for hardware performance counters, as
@@ -258,5 +369,113 @@ properties:
            in commit 2e5236 ("Ztso is now ratified.") of the
            riscv-isa-manual.

        - const: zvbb
          description:
            The standard Zvbb extension for vectored basic bit-manipulation
            instructions, as ratified in commit 56ed795 ("Update
            riscv-crypto-spec-vector.adoc") of riscv-crypto.

        - const: zvbc
          description:
            The standard Zvbc extension for vectored carryless multiplication
            instructions, as ratified in commit 56ed795 ("Update
            riscv-crypto-spec-vector.adoc") of riscv-crypto.

        - const: zvfh
          description:
            The standard Zvfh extension for vectored half-precision
            floating-point instructions, as ratified in commit e2ccd05
            ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.

        - const: zvfhmin
          description:
            The standard Zvfhmin extension for vectored minimal half-precision
            floating-point instructions, as ratified in commit e2ccd05
            ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.

        - const: zvkb
          description:
            The standard Zvkb extension for vector cryptography bit-manipulation
            instructions, as ratified in commit 56ed795 ("Update
            riscv-crypto-spec-vector.adoc") of riscv-crypto.

        - const: zvkg
          description:
            The standard Zvkg extension for vector GCM/GMAC instructions, as
            ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
            of riscv-crypto.

        - const: zvkn
          description:
            The standard Zvkn extension for NIST algorithm suite instructions, as
            ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
            of riscv-crypto.

        - const: zvknc
          description:
            The standard Zvknc extension for NIST algorithm suite with carryless
            multiply instructions, as ratified in commit 56ed795 ("Update
            riscv-crypto-spec-vector.adoc") of riscv-crypto.

        - const: zvkned
          description:
            The standard Zvkned extension for Vector AES block cipher
            instructions, as ratified in commit 56ed795 ("Update
            riscv-crypto-spec-vector.adoc") of riscv-crypto.

        - const: zvkng
          description:
            The standard Zvkng extension for NIST algorithm suite with GCM
            instructions, as ratified in commit 56ed795 ("Update
            riscv-crypto-spec-vector.adoc") of riscv-crypto.

        - const: zvknha
          description: |
            The standard Zvknha extension for NIST suite: vector SHA-2 secure,
            hash (SHA-256 only) instructions, as ratified in commit
            56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.

        - const: zvknhb
          description: |
            The standard Zvknhb extension for NIST suite: vector SHA-2 secure,
            hash (SHA-256 and SHA-512) instructions, as ratified in commit
            56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.

        - const: zvks
          description:
            The standard Zvks extension for ShangMi algorithm suite
            instructions, as ratified in commit 56ed795 ("Update
            riscv-crypto-spec-vector.adoc") of riscv-crypto.

        - const: zvksc
          description:
            The standard Zvksc extension for ShangMi algorithm suite with
            carryless multiplication instructions, as ratified in commit 56ed795
            ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.

        - const: zvksed
          description: |
            The standard Zvksed extension for ShangMi suite: SM4 block cipher
            instructions, as ratified in commit 56ed795 ("Update
            riscv-crypto-spec-vector.adoc") of riscv-crypto.

        - const: zvksh
          description: |
            The standard Zvksh extension for ShangMi suite: SM3 secure hash
            instructions, as ratified in commit 56ed795 ("Update
            riscv-crypto-spec-vector.adoc") of riscv-crypto.

        - const: zvksg
          description:
            The standard Zvksg extension for ShangMi algorithm suite with GCM
            instructions, as ratified in commit 56ed795 ("Update
            riscv-crypto-spec-vector.adoc") of riscv-crypto.

        - const: zvkt
          description:
            The standard Zvkt extension for vector data-independent execution
            latency, as ratified in commit 56ed795 ("Update
            riscv-crypto-spec-vector.adoc") of riscv-crypto.

additionalProperties: true
...
+2 −0
Original line number Diff line number Diff line
@@ -151,6 +151,8 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,

extern pgd_t swapper_pg_dir[PTRS_PER_PGD];

#define pgdp_get(pgpd)		READ_ONCE(*pgdp)

#define pud_page(pud)		pmd_page(__pmd(pud_val(pud)))
#define pud_write(pud)		pmd_write(__pmd(pud_val(pud)))

+4 −3
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ config RISCV
	select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
	select ARCH_WANT_LD_ORPHAN_WARN if !XIP_KERNEL
	select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP
	select ARCH_WANTS_NO_INSTR
	select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
	select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU
	select BUILDTIME_TABLE_SORT if MMU
@@ -902,13 +903,13 @@ config RISCV_ISA_FALLBACK
	  on the replacement properties, "riscv,isa-base" and
	  "riscv,isa-extensions".

endmenu # "Boot options"

config BUILTIN_DTB
	bool
	bool "Built-in device tree"
	depends on OF && NONPORTABLE
	default y if XIP_KERNEL

endmenu # "Boot options"

config PORTABLE
	bool
	default !NONPORTABLE
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