Commit 0afd104f authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvmarm-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD 

KVM/arm64 updates for 6.15

 - Nested virtualization support for VGICv3, giving the nested
   hypervisor control of the VGIC hardware when running an L2 VM

 - Removal of 'late' nested virtualization feature register masking,
   making the supported feature set directly visible to userspace

 - Support for emulating FEAT_PMUv3 on Apple silicon, taking advantage
   of an IMPLEMENTATION DEFINED trap that covers all PMUv3 registers

 - Paravirtual interface for discovering the set of CPU implementations
   where a VM may run, addressing a longstanding issue of guest CPU
   errata awareness in big-little systems and cross-implementation VM
   migration

 - Userspace control of the registers responsible for identifying a
   particular CPU implementation (MIDR_EL1, REVIDR_EL1, AIDR_EL1),
   allowing VMs to be migrated cross-implementation

 - pKVM updates, including support for tracking stage-2 page table
   allocations in the protected hypervisor in the 'SecPageTable' stat

 - Fixes to vPMU, ensuring that userspace updates to the vPMU after
   KVM_RUN are reflected into the backing perf events
parents c0f99fb4 369c0122

Documentation/virt/kvm/api.rst

+18 −0
Original line number Diff line number Diff line
@@ -8262,6 +8262,24 @@ KVM exits with the register state of either the L1 or L2 guest 
depending on which executed at the time of an exit. Userspace must

take care to differentiate between these cases.



7.37 KVM_CAP_ARM_WRITABLE_IMP_ID_REGS

-------------------------------------



:Architectures: arm64

:Target: VM

:Parameters: None

:Returns: 0 on success, -EINVAL if vCPUs have been created before enabling this

          capability.



This capability changes the behavior of the registers that identify a PE

implementation of the Arm architecture: MIDR_EL1, REVIDR_EL1, and AIDR_EL1.

By default, these registers are visible to userspace but treated as invariant.



When this capability is enabled, KVM allows userspace to change the

aforementioned registers before the first KVM_RUN. These registers are VM

scoped, meaning that the same set of values are presented on all vCPUs in a

given VM.



8. Other capabilities.

======================

Documentation/virt/kvm/arm/fw-pseudo-registers.rst

+14 −1
Original line number Diff line number Diff line
@@ -116,7 +116,7 @@ The pseudo-firmware bitmap register are as follows: 
      ARM DEN0057A.



* KVM_REG_ARM_VENDOR_HYP_BMAP:

    Controls the bitmap of the Vendor specific Hypervisor Service Calls.

    Controls the bitmap of the Vendor specific Hypervisor Service Calls[0-63].



  The following bits are accepted:
@@ -127,6 +127,19 @@ The pseudo-firmware bitmap register are as follows: 
    Bit-1: KVM_REG_ARM_VENDOR_HYP_BIT_PTP:

      The bit represents the Precision Time Protocol KVM service.



* KVM_REG_ARM_VENDOR_HYP_BMAP_2:

    Controls the bitmap of the Vendor specific Hypervisor Service Calls[64-127].



  The following bits are accepted:



    Bit-0: KVM_REG_ARM_VENDOR_HYP_BIT_DISCOVER_IMPL_VER

      This represents the ARM_SMCCC_VENDOR_HYP_KVM_DISCOVER_IMPL_VER_FUNC_ID

      function-id. This is reset to 0.



    Bit-1: KVM_REG_ARM_VENDOR_HYP_BIT_DISCOVER_IMPL_CPUS

      This represents the ARM_SMCCC_VENDOR_HYP_KVM_DISCOVER_IMPL_CPUS_FUNC_ID

      function-id. This is reset to 0.



Errors:



    =======  =============================================================

Documentation/virt/kvm/arm/hypercalls.rst

+59 −0
Original line number Diff line number Diff line
@@ -142,3 +142,62 @@ region is equal to the memory protection granule advertised by 
|                     |          |    +---------------------------------------------+

|                     |          |    | ``INVALID_PARAMETER (-3)``                  |

+---------------------+----------+----+---------------------------------------------+



``ARM_SMCCC_VENDOR_HYP_KVM_DISCOVER_IMPL_VER_FUNC_ID``

-------------------------------------------------------

Request the target CPU implementation version information and the number of target

implementations for the Guest VM.



+---------------------+-------------------------------------------------------------+

| Presence:           | Optional;  KVM/ARM64 Guests only                            |

+---------------------+-------------------------------------------------------------+

| Calling convention: | HVC64                                                       |

+---------------------+----------+--------------------------------------------------+

| Function ID:        | (uint32) | 0xC6000040                                       |

+---------------------+----------+--------------------------------------------------+

| Arguments:          | None                                                        |

+---------------------+----------+----+---------------------------------------------+

| Return Values:      | (int64)  | R0 | ``SUCCESS (0)``                             |

|                     |          |    +---------------------------------------------+

|                     |          |    | ``NOT_SUPPORTED (-1)``                      |

|                     +----------+----+---------------------------------------------+

|                     | (uint64) | R1 | Bits [63:32] Reserved/Must be zero          |

|                     |          |    +---------------------------------------------+

|                     |          |    | Bits [31:16] Major version                  |

|                     |          |    +---------------------------------------------+

|                     |          |    | Bits [15:0] Minor version                   |

|                     +----------+----+---------------------------------------------+

|                     | (uint64) | R2 | Number of target implementations            |

|                     +----------+----+---------------------------------------------+

|                     | (uint64) | R3 | Reserved / Must be zero                     |

+---------------------+----------+----+---------------------------------------------+



``ARM_SMCCC_VENDOR_HYP_KVM_DISCOVER_IMPL_CPUS_FUNC_ID``

-------------------------------------------------------



Request the target CPU implementation information for the Guest VM. The Guest kernel

will use this information to enable the associated errata.



+---------------------+-------------------------------------------------------------+

| Presence:           | Optional;  KVM/ARM64 Guests only                            |

+---------------------+-------------------------------------------------------------+

| Calling convention: | HVC64                                                       |

+---------------------+----------+--------------------------------------------------+

| Function ID:        | (uint32) | 0xC6000041                                       |

+---------------------+----------+----+---------------------------------------------+

| Arguments:          | (uint64) | R1 | selected implementation index               |

|                     +----------+----+---------------------------------------------+

|                     | (uint64) | R2 | Reserved / Must be zero                     |

|                     +----------+----+---------------------------------------------+

|                     | (uint64) | R3 | Reserved / Must be zero                     |

+---------------------+----------+----+---------------------------------------------+

| Return Values:      | (int64)  | R0 | ``SUCCESS (0)``                             |

|                     |          |    +---------------------------------------------+

|                     |          |    | ``INVALID_PARAMETER (-3)``                  |

|                     +----------+----+---------------------------------------------+

|                     | (uint64) | R1 | MIDR_EL1 of the selected implementation     |

|                     +----------+----+---------------------------------------------+

|                     | (uint64) | R2 | REVIDR_EL1 of the selected implementation   |

|                     +----------+----+---------------------------------------------+

|                     | (uint64) | R3 | AIDR_EL1  of the selected implementation    |

+---------------------+----------+----+---------------------------------------------+

Documentation/virt/kvm/devices/arm-vgic-its.rst

+4 −1
Original line number Diff line number Diff line
@@ -126,7 +126,8 @@ KVM_DEV_ARM_VGIC_GRP_ITS_REGS 
ITS Restore Sequence:

---------------------



The following ordering must be followed when restoring the GIC and the ITS:

The following ordering must be followed when restoring the GIC, ITS, and

KVM_IRQFD assignments:



a) restore all guest memory and create vcpus

b) restore all redistributors
@@ -139,6 +140,8 @@ d) restore the ITS in the following order: 
     3. Load the ITS table data (KVM_DEV_ARM_ITS_RESTORE_TABLES)

     4. Restore GITS_CTLR



e) restore KVM_IRQFD assignments for MSIs



Then vcpus can be started.



ITS Table ABI REV0:

Documentation/virt/kvm/devices/arm-vgic-v3.rst

+11 −1
Original line number Diff line number Diff line
@@ -291,8 +291,18 @@ Groups: 
      |    Aff3    |    Aff2    |    Aff1    |    Aff0    |



  Errors:



    =======  =============================================

    -EINVAL  vINTID is not multiple of 32 or info field is

	     not VGIC_LEVEL_INFO_LINE_LEVEL

    =======  =============================================



  KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ

   Attributes:



    The attr field of kvm_device_attr encodes the following values:



      bits:     | 31   ....    5 | 4  ....  0 |

      values:   |      RES0      |   vINTID   |



    The vINTID specifies which interrupt is generated when the vGIC

    must generate a maintenance interrupt. This must be a PPI.