Commit 0b80b3c0 authored by Johan Hovold's avatar Johan Hovold Committed by Bjorn Andersson
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arm64: dts: qcom: x1e80100: fix PCIe5 PHY clocks 



Add the missing clkref enable and pipediv2 clocks to the PCIe5 PHY.

Fixes: 62ab23e1 ("arm64: dts: qcom: x1e80100: add PCIe5 nodes")
Signed-off-by: default avatarJohan Hovold <johan+linaro@kernel.org>
Reviewed-by: default avatarKonrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/r/20240916082307.29393-4-johan+linaro@kernel.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 27727cb6

arch/arm64/boot/dts/qcom/x1e80100.dtsi

+5 −3
Original line number Diff line number Diff line
@@ -3126,14 +3126,16 @@ pcie5_phy: phy@1c06000 { 


			clocks = <&gcc GCC_PCIE_5_AUX_CLK>,

				 <&gcc GCC_PCIE_5_CFG_AHB_CLK>,

				 <&rpmhcc RPMH_CXO_CLK>,

				 <&tcsr TCSR_PCIE_2L_5_CLKREF_EN>,

				 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>,

				 <&gcc GCC_PCIE_5_PIPE_CLK>;

				 <&gcc GCC_PCIE_5_PIPE_CLK>,

				 <&gcc GCC_PCIE_5_PIPEDIV2_CLK>;

			clock-names = "aux",

				      "cfg_ahb",

				      "ref",

				      "rchng",

				      "pipe";

				      "pipe",

				      "pipediv2";



			resets = <&gcc GCC_PCIE_5_PHY_BCR>;

			reset-names = "phy";