Commit 0c5ade74 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branches 'for-next/reorg-va-space', 'for-next/rust-for-arm64',... 

Merge branches 'for-next/reorg-va-space', 'for-next/rust-for-arm64', 'for-next/misc', 'for-next/daif-cleanup', 'for-next/kselftest', 'for-next/documentation', 'for-next/sysreg' and 'for-next/dpisa', remote-tracking branch 'arm64/for-next/perf' into for-next/core

* arm64/for-next/perf: (39 commits)
  docs: perf: Fix build warning of hisi-pcie-pmu.rst
  perf: starfive: Only allow COMPILE_TEST for 64-bit architectures
  MAINTAINERS: Add entry for StarFive StarLink PMU
  docs: perf: Add description for StarFive's StarLink PMU
  dt-bindings: perf: starfive: Add JH8100 StarLink PMU
  perf: starfive: Add StarLink PMU support
  docs: perf: Update usage for target filter of hisi-pcie-pmu
  drivers/perf: hisi_pcie: Merge find_related_event() and get_event_idx()
  drivers/perf: hisi_pcie: Relax the check on related events
  drivers/perf: hisi_pcie: Check the target filter properly
  drivers/perf: hisi_pcie: Add more events for counting TLP bandwidth
  drivers/perf: hisi_pcie: Fix incorrect counting under metric mode
  drivers/perf: hisi_pcie: Introduce hisi_pcie_pmu_get_event_ctrl_val()
  drivers/perf: hisi_pcie: Rename hisi_pcie_pmu_{config,clear}_filter()
  drivers/perf: hisi: Enable HiSilicon Erratum 162700402 quirk for HIP09
  perf/arm_cspmu: Add devicetree support
  dt-bindings/perf: Add Arm CoreSight PMU
  perf/arm_cspmu: Simplify counter reset
  perf/arm_cspmu: Simplify attribute groups
  perf/arm_cspmu: Simplify initialisation
  ...

* for-next/reorg-va-space:
  : Reorganise the arm64 kernel VA space in preparation for LPA2 support
  : (52-bit VA/PA).
  arm64: kaslr: Adjust randomization range dynamically
  arm64: mm: Reclaim unused vmemmap region for vmalloc use
  arm64: vmemmap: Avoid base2 order of struct page size to dimension region
  arm64: ptdump: Discover start of vmemmap region at runtime
  arm64: ptdump: Allow all region boundaries to be defined at boot time
  arm64: mm: Move fixmap region above vmemmap region
  arm64: mm: Move PCI I/O emulation region above the vmemmap region

* for-next/rust-for-arm64:
  : Enable Rust support for arm64
  arm64: rust: Enable Rust support for AArch64
  rust: Refactor the build target to allow the use of builtin targets

* for-next/misc:
  : Miscellaneous arm64 patches
  ARM64: Dynamically allocate cpumasks and increase supported CPUs to 512
  arm64: Remove enable_daif macro
  arm64/hw_breakpoint: Directly use ESR_ELx_WNR for an watchpoint exception
  arm64: cpufeatures: Clean up temporary variable to simplify code
  arm64: Update setup_arch() comment on interrupt masking
  arm64: remove unnecessary ifdefs around is_compat_task()
  arm64: ftrace: Don't forbid CALL_OPS+CC_OPTIMIZE_FOR_SIZE with Clang
  arm64/sme: Ensure that all fields in SMCR_EL1 are set to known values
  arm64/sve: Ensure that all fields in ZCR_EL1 are set to known values
  arm64/sve: Document that __SVE_VQ_MAX is much larger than needed
  arm64: make member of struct pt_regs and it's offset macro in the same order
  arm64: remove unneeded BUILD_BUG_ON assertion
  arm64: kretprobes: acquire the regs via a BRK exception
  arm64: io: permit offset addressing
  arm64: errata: Don't enable workarounds for "rare" errata by default

* for-next/daif-cleanup:
  : Clean up DAIF handling for EL0 returns
  arm64: Unmask Debug + SError in do_notify_resume()
  arm64: Move do_notify_resume() to entry-common.c
  arm64: Simplify do_notify_resume() DAIF masking

* for-next/kselftest:
  : Miscellaneous arm64 kselftest patches
  kselftest/arm64: Test that ptrace takes effect in the target process

* for-next/documentation:
  : arm64 documentation patches
  arm64/sme: Remove spurious 'is' in SME documentation
  arm64/fp: Clarify effect of setting an unsupported system VL
  arm64/sme: Fix cut'n'paste in ABI document
  arm64/sve: Remove bitrotted comment about syscall behaviour

* for-next/sysreg:
  : sysreg updates
  arm64/sysreg: Update ID_AA64DFR0_EL1 register
  arm64/sysreg: Update ID_DFR0_EL1 register fields
  arm64/sysreg: Add register fields for ID_AA64DFR1_EL1

* for-next/dpisa:
  : Support for 2023 dpISA extensions
  kselftest/arm64: Add 2023 DPISA hwcap test coverage
  kselftest/arm64: Add basic FPMR test
  kselftest/arm64: Handle FPMR context in generic signal frame parser
  arm64/hwcap: Define hwcaps for 2023 DPISA features
  arm64/ptrace: Expose FPMR via ptrace
  arm64/signal: Add FPMR signal handling
  arm64/fpsimd: Support FEAT_FPMR
  arm64/fpsimd: Enable host kernel access to FPMR
  arm64/cpufeature: Hook new identification registers up to cpufeature
parents b037e40a 3567fa63 724a75ac 0499a783 97d935fa c745b15c e47c18c3 358fee29 44d10c27

Documentation/arch/arm64/elf_hwcaps.rst

+49 −0
Original line number Diff line number Diff line
@@ -317,6 +317,55 @@ HWCAP2_LRCPC3 
HWCAP2_LSE128

    Functionality implied by ID_AA64ISAR0_EL1.Atomic == 0b0011.



HWCAP2_FPMR

    Functionality implied by ID_AA64PFR2_EL1.FMR == 0b0001.



HWCAP2_LUT

    Functionality implied by ID_AA64ISAR2_EL1.LUT == 0b0001.



HWCAP2_FAMINMAX

    Functionality implied by ID_AA64ISAR3_EL1.FAMINMAX == 0b0001.



HWCAP2_F8CVT

    Functionality implied by ID_AA64FPFR0_EL1.F8CVT == 0b1.



HWCAP2_F8FMA

    Functionality implied by ID_AA64FPFR0_EL1.F8FMA == 0b1.



HWCAP2_F8DP4

    Functionality implied by ID_AA64FPFR0_EL1.F8DP4 == 0b1.



HWCAP2_F8DP2

    Functionality implied by ID_AA64FPFR0_EL1.F8DP2 == 0b1.



HWCAP2_F8E4M3

    Functionality implied by ID_AA64FPFR0_EL1.F8E4M3 == 0b1.



HWCAP2_F8E5M2

    Functionality implied by ID_AA64FPFR0_EL1.F8E5M2 == 0b1.



HWCAP2_SME_LUTV2

    Functionality implied by ID_AA64SMFR0_EL1.LUTv2 == 0b1.



HWCAP2_SME_F8F16

    Functionality implied by ID_AA64SMFR0_EL1.F8F16 == 0b1.



HWCAP2_SME_F8F32

    Functionality implied by ID_AA64SMFR0_EL1.F8F32 == 0b1.



HWCAP2_SME_SF8FMA

    Functionality implied by ID_AA64SMFR0_EL1.SF8FMA == 0b1.



HWCAP2_SME_SF8DP4

    Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1.



HWCAP2_SME_SF8DP2

    Functionality implied by ID_AA64SMFR0_EL1.SF8DP2 == 0b1.



HWCAP2_SME_SF8DP4

    Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1.





4. Unused AT_HWCAP bits

-----------------------

Documentation/arch/arm64/silicon-errata.rst

+3 −2
Original line number Diff line number Diff line
@@ -35,8 +35,9 @@ can be triggered by Linux). 
For software workarounds that may adversely impact systems unaffected by

the erratum in question, a Kconfig entry is added under "Kernel

Features" -> "ARM errata workarounds via the alternatives framework".

These are enabled by default and patched in at runtime when an affected

CPU is detected. For less-intrusive workarounds, a Kconfig option is not

With the exception of workarounds for errata deemed "rare" by Arm, these

are enabled by default and patched in at runtime when an affected CPU is

detected. For less-intrusive workarounds, a Kconfig option is not

available and the code is structured (preferably with a comment) in such

a way that the erratum will not be hit.

Documentation/arch/arm64/sme.rst

+5 −6
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ model features for SME is included in Appendix A. 
2.  Vector lengths

------------------



SME defines a second vector length similar to the SVE vector length which is

SME defines a second vector length similar to the SVE vector length which

controls the size of the streaming mode SVE vectors and the ZA matrix array.

The ZA matrix is square with each side having as many bytes as a streaming

mode SVE vector.
@@ -238,12 +238,12 @@ prctl(PR_SME_SET_VL, unsigned long arg) 
      bits of Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become

      unspecified, including both streaming and non-streaming SVE state.

      Calling PR_SME_SET_VL with vl equal to the thread's current vector

      length, or calling PR_SME_SET_VL with the PR_SVE_SET_VL_ONEXEC flag,

      length, or calling PR_SME_SET_VL with the PR_SME_SET_VL_ONEXEC flag,

      does not constitute a change to the vector length for this purpose.



    * Changing the vector length causes PSTATE.ZA and PSTATE.SM to be cleared.

      Calling PR_SME_SET_VL with vl equal to the thread's current vector

      length, or calling PR_SME_SET_VL with the PR_SVE_SET_VL_ONEXEC flag,

      length, or calling PR_SME_SET_VL with the PR_SME_SET_VL_ONEXEC flag,

      does not constitute a change to the vector length for this purpose.
@@ -379,9 +379,8 @@ The regset data starts with struct user_za_header, containing: 
/proc/sys/abi/sme_default_vector_length



    Writing the text representation of an integer to this file sets the system

    default vector length to the specified value, unless the value is greater

    than the maximum vector length supported by the system in which case the

    default vector length is set to that maximum.

    default vector length to the specified value rounded to a supported value

    using the same rules as for setting vector length via PR_SME_SET_VL.



    The result can be determined by reopening the file and reading its

    contents.

Documentation/arch/arm64/sve.rst

+2 −8
Original line number Diff line number Diff line
@@ -117,11 +117,6 @@ the SVE instruction set architecture. 
* The SVE registers are not used to pass arguments to or receive results from

  any syscall.



* In practice the affected registers/bits will be preserved or will be replaced

  with zeros on return from a syscall, but userspace should not make

  assumptions about this.  The kernel behaviour may vary on a case-by-case

  basis.



* All other SVE state of a thread, including the currently configured vector

  length, the state of the PR_SVE_VL_INHERIT flag, and the deferred vector

  length (if any), is preserved across all syscalls, subject to the specific
@@ -428,9 +423,8 @@ The regset data starts with struct user_sve_header, containing: 
/proc/sys/abi/sve_default_vector_length



    Writing the text representation of an integer to this file sets the system

    default vector length to the specified value, unless the value is greater

    than the maximum vector length supported by the system in which case the

    default vector length is set to that maximum.

    default vector length to the specified value rounded to a supported value

    using the same rules as for setting vector length via PR_SVE_SET_VL.



    The result can be determined by reopening the file and reading its

    contents.

Documentation/rust/arch-support.rst

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ support corresponds to ``S`` values in the ``MAINTAINERS`` file. 
=============  ================  ==============================================

Architecture   Level of support  Constraints

=============  ================  ==============================================

``arm64``      Maintained        Little Endian only.

``loongarch``  Maintained        -

``um``         Maintained        ``x86_64`` only.

``x86``        Maintained        ``x86_64`` only.