Commit 0d9a49a2 authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amd/pm: Initialize allowed feature list 



Instead of returning feature bit mask of allowed features, initialize
the allowed features in the callback implementation itself.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarAsad Kamal <asad.kamal@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 156c0ab1

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

+3 −14
Original line number Diff line number Diff line
@@ -691,11 +691,8 @@ static int smu_sys_set_pp_table(void *handle, 
	return ret;

}



static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)

static int smu_init_driver_allowed_feature_mask(struct smu_context *smu)

{

	uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];

	int ret = 0;



	/*

	 * With SCPM enabled, the allowed featuremasks setting(via

	 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted.
@@ -710,15 +707,7 @@ static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 


	smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);



	ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,

					     SMU_FEATURE_MAX/32);

	if (ret)

		return ret;



	smu_feature_list_add_bits(smu, SMU_FEATURE_LIST_ALLOWED,

				  (unsigned long *)allowed_feature_mask);



	return ret;

	return smu_init_allowed_features(smu);

}



static int smu_set_funcs(struct amdgpu_device *adev)
@@ -1949,7 +1938,7 @@ static int smu_hw_init(struct amdgpu_ip_block *ip_block) 
	if (!smu->pm_enabled)

		return 0;



	ret = smu_get_driver_allowed_feature_mask(smu);

	ret = smu_init_driver_allowed_feature_mask(smu);

	if (ret)

		return ret;

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

+3 −21
Original line number Diff line number Diff line
@@ -812,11 +812,10 @@ struct pptable_funcs { 
	int (*run_btc)(struct smu_context *smu);



	/**

	 * @get_allowed_feature_mask: Get allowed feature mask.

	 * &feature_mask: Array to store feature mask.

	 * &num: Elements in &feature_mask.

	 * @init_allowed_features: Initialize allowed features bitmap.

	 * Directly sets allowed features using smu_feature wrapper functions.

	 */

	int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);

	int (*init_allowed_features)(struct smu_context *smu);



	/**

	 * @get_current_power_state: Get the current power state.
@@ -2052,14 +2051,6 @@ static inline void smu_feature_bits_copy(struct smu_feature_bits *dst, 
	bitmap_copy(dst->bits, src, nbits);

}



static inline void smu_feature_bits_or(struct smu_feature_bits *dst,

				       const struct smu_feature_bits *src1,

				       const unsigned long *src2,

				       unsigned int nbits)

{

	bitmap_or(dst->bits, src1->bits, src2, nbits);

}



static inline struct smu_feature_bits *

__smu_feature_get_list(struct smu_context *smu, enum smu_feature_list list)

{
@@ -2128,15 +2119,6 @@ static inline void smu_feature_list_set_bits(struct smu_context *smu, 
			      smu->smu_feature.feature_num);

}



static inline void smu_feature_list_add_bits(struct smu_context *smu,

					     enum smu_feature_list list,

					     const unsigned long *src)

{

	struct smu_feature_bits *bits = __smu_feature_get_list(smu, list);



	smu_feature_bits_or(bits, bits, src, smu->smu_feature.feature_num);

}



static inline void smu_feature_list_to_arr32(struct smu_context *smu,

					     enum smu_feature_list list,

					     uint32_t *arr)

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

+3 −8
Original line number Diff line number Diff line
@@ -345,14 +345,9 @@ static int arcturus_init_smc_tables(struct smu_context *smu) 
}



static int

arcturus_get_allowed_feature_mask(struct smu_context *smu,

				  uint32_t *feature_mask, uint32_t num)

arcturus_init_allowed_features(struct smu_context *smu)

{

	if (num > 2)

		return -EINVAL;



	/* pptable will handle the features to enable */

	memset(feature_mask, 0xFF, sizeof(uint32_t) * num);

	smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);



	return 0;

}
@@ -1877,7 +1872,7 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, 


static const struct pptable_funcs arcturus_ppt_funcs = {

	/* init dpm */

	.get_allowed_feature_mask = arcturus_get_allowed_feature_mask,

	.init_allowed_features = arcturus_init_allowed_features,

	/* btc */

	.run_btc = arcturus_run_btc,

	/* dpm/clk tables */

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

+43 −49
Original line number Diff line number Diff line
@@ -275,89 +275,83 @@ static bool is_asic_secure(struct smu_context *smu) 
}



static int

navi10_get_allowed_feature_mask(struct smu_context *smu,

				  uint32_t *feature_mask, uint32_t num)

navi10_init_allowed_features(struct smu_context *smu)

{

	struct amdgpu_device *adev = smu->adev;



	if (num > 2)

		return -EINVAL;



	memset(feature_mask, 0, sizeof(uint32_t) * num);



	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)

				| FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)

				| FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)

				| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)

				| FEATURE_MASK(FEATURE_PPT_BIT)

				| FEATURE_MASK(FEATURE_TDC_BIT)

				| FEATURE_MASK(FEATURE_GFX_EDC_BIT)

				| FEATURE_MASK(FEATURE_APCC_PLUS_BIT)

				| FEATURE_MASK(FEATURE_VR0HOT_BIT)

				| FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)

				| FEATURE_MASK(FEATURE_THERMAL_BIT)

				| FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)

				| FEATURE_MASK(FEATURE_DS_LCLK_BIT)

				| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)

				| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)

				| FEATURE_MASK(FEATURE_BACO_BIT)

				| FEATURE_MASK(FEATURE_GFX_SS_BIT)

				| FEATURE_MASK(FEATURE_APCC_DFLL_BIT)

				| FEATURE_MASK(FEATURE_FW_CTF_BIT)

				| FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT)

				| FEATURE_MASK(FEATURE_TEMP_DEPENDENT_VMIN_BIT);

	smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);



	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_PREFETCHER_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_RSMU_SMN_CG_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_PPT_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TDC_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_EDC_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_PLUS_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THERMAL_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_LED_DISPLAY_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_DCEFCLK_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_SS_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_DFLL_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_OUT_OF_BAND_MONITOR_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TEMP_DEPENDENT_VMIN_BIT);



	if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT);



	if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT);



	if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCEFCLK_BIT);



	if (adev->pm.pp_feature & PP_ULV_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT);



	if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT);



	if (adev->pm.pp_feature & PP_GFXOFF_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT);



	if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MMHUB_PG_BIT);



	if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_PG_BIT);



	if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VCN_PG_BIT);



	if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_JPEG_PG_BIT);



	if (smu->dc_controlled_by_gpio)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ACDC_BIT);



	if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT);



	/* DPM UCLK enablement should be skipped for navi10 A0 secure board */

	if (!(is_asic_secure(smu) &&

	      (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&

	      (adev->rev_id == 0)) &&

	    (adev->pm.pp_feature & PP_MCLK_DPM_MASK))

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)

				| FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)

				| FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);

	    (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT);

	}



	/* DS SOCCLK enablement should be skipped for navi10 A0 secure board */

	if (is_asic_secure(smu) &&

	    (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&

	    (adev->rev_id == 0))

		*(uint64_t *)feature_mask &=

				~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);

		smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT);



	return 0;

}
@@ -3277,7 +3271,7 @@ static int navi10_set_config_table(struct smu_context *smu, 
}



static const struct pptable_funcs navi10_ppt_funcs = {

	.get_allowed_feature_mask = navi10_get_allowed_feature_mask,

	.init_allowed_features = navi10_init_allowed_features,

	.set_default_dpm_table = navi10_set_default_dpm_table,

	.dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,

	.dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+43 −46
Original line number Diff line number Diff line
@@ -276,85 +276,82 @@ static const uint8_t sienna_cichlid_throttler_map[] = { 
};



static int

sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,

				  uint32_t *feature_mask, uint32_t num)

sienna_cichlid_init_allowed_features(struct smu_context *smu)

{

	struct amdgpu_device *adev = smu->adev;



	if (num > 2)

		return -EINVAL;



	memset(feature_mask, 0, sizeof(uint32_t) * num);



	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)

				| FEATURE_MASK(FEATURE_DPM_FCLK_BIT)

				| FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)

				| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)

				| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)

				| FEATURE_MASK(FEATURE_DS_FCLK_BIT)

				| FEATURE_MASK(FEATURE_DS_UCLK_BIT)

				| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)

				| FEATURE_MASK(FEATURE_DF_CSTATE_BIT)

				| FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)

				| FEATURE_MASK(FEATURE_GFX_SS_BIT)

				| FEATURE_MASK(FEATURE_VR0HOT_BIT)

				| FEATURE_MASK(FEATURE_PPT_BIT)

				| FEATURE_MASK(FEATURE_TDC_BIT)

				| FEATURE_MASK(FEATURE_BACO_BIT)

				| FEATURE_MASK(FEATURE_APCC_DFLL_BIT)

				| FEATURE_MASK(FEATURE_FW_CTF_BIT)

				| FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)

				| FEATURE_MASK(FEATURE_THERMAL_BIT)

				| FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);

	smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED);



	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_PREFETCHER_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_FCLK_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_DCEFCLK_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_FCLK_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_UCLK_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DF_CSTATE_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_RSMU_SMN_CG_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_SS_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_PPT_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TDC_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_DFLL_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THERMAL_BIT);

	smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_OUT_OF_BAND_MONITOR_BIT);



	if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFX_GPO_BIT);

	}



	if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&

	    (amdgpu_ip_version(adev, MP1_HWIP, 0) > IP_VERSION(11, 0, 7)) &&

	    !(adev->flags & AMD_IS_APU))

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_DCS_BIT);



	if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)

					| FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)

					| FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);

	if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT);

	}



	if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT);



	if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCEFCLK_BIT);



	if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT);



	if (adev->pm.pp_feature & PP_ULV_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT);



	if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT);



	if (adev->pm.pp_feature & PP_GFXOFF_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT);



	if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_PG_BIT);



	if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MMHUB_PG_BIT);



	if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||

	    smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MM_DPM_PG_BIT);



	if (smu->dc_controlled_by_gpio)

       *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ACDC_BIT);



	if (amdgpu_device_should_use_aspm(adev))

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);

		smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT);



	return 0;

}
@@ -3085,7 +3082,7 @@ static int sienna_cichlid_mode2_reset(struct smu_context *smu) 
}



static const struct pptable_funcs sienna_cichlid_ppt_funcs = {

	.get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,

	.init_allowed_features = sienna_cichlid_init_allowed_features,

	.set_default_dpm_table = sienna_cichlid_set_default_dpm_table,

	.dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,

	.dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,