Commit 0e2ebfe2 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx12: dump full CP packet header FIFOs 



In dev core dump, dump the full header fifo for
each queue. Each FIFO has 8 entries.

Reviewed-by: default avatarPierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: default avatarSunil Khatri <sunil.khatri@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent eb15a5d1

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

+35 −6
Original line number Diff line number Diff line
@@ -133,11 +133,14 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { 
	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR),



	/* cp header registers */

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),

	/* SE status registers */

	SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
@@ -186,7 +189,16 @@ static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = { 
	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS)

	SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS),

	/* cp header registers */

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),

};



static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = {
@@ -215,7 +227,24 @@ static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 
	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ)

	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),

	/* cp header registers */

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

	SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),

};



static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = {