Commit 0edee819 authored by Kajol Jain's avatar Kajol Jain Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events power10: Move the JSON/events 



Move some of the JSON/events from others.json to more appropriate JSON
files for power10 platform.

Reviewed-by: default avatarIan Rogers <irogers@google.com>
Signed-off-by: default avatarKajol Jain <kjain@linux.ibm.com>
Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Cc: Disha Goel <disgoel@linux.vnet.ibm.com>
Cc: Hari Bathini <hbathini@linux.ibm.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: linuxppc-dev@lists.ozlabs.org
Link: https://lore.kernel.org/r/20240827053206.538814-2-kjain@linux.ibm.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent c5d50457

tools/perf/pmu-events/arch/powerpc/power10/cache.json

+15 −0
Original line number Diff line number Diff line 
[

  {

    "EventCode": "0x1002C",

    "EventName": "PM_LD_PREFETCH_CACHE_LINE_MISS",

    "BriefDescription": "The L1 cache was reloaded with a line that fulfills a prefetch request."

  },

  {

    "EventCode": "0x200FD",

    "EventName": "PM_L1_ICACHE_MISS",

    "BriefDescription": "Demand instruction cache miss."

  },

  {

    "EventCode": "0x30068",

    "EventName": "PM_L1_ICACHE_RELOADED_PREF",

    "BriefDescription": "Counts all instruction cache prefetch reloads (includes demand turned into prefetch)."

  },

  {

    "EventCode": "0x300F4",

    "EventName": "PM_RUN_INST_CMPL_CONC",

tools/perf/pmu-events/arch/powerpc/power10/datasource.json

+15 −0
Original line number Diff line number Diff line 
[

  {

    "EventCode": "0x1505E",

    "EventName": "PM_LD_HIT_L1",

    "BriefDescription": "Load  finished without experiencing an L1 miss."

  },

  {

    "EventCode": "0x100FC",

    "EventName": "PM_LD_REF_L1",

    "BriefDescription": "All L1 D cache load references counted at finish, gated by reject. In P9 and earlier this event counted only cacheable loads but in P10 both cacheable and non-cacheable loads are included."

  },

  {

    "EventCode": "0x200FE",

    "EventName": "PM_DATA_FROM_L2MISS",
@@ -9,6 +19,11 @@ 
    "EventName": "PM_DATA_FROM_L3MISS",

    "BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss."

  },

  {

    "EventCode": "0x400F0",

    "EventName": "PM_LD_DEMAND_MISS_L1_FIN",

    "BriefDescription": "Load missed L1, counted at finish time."

  },

  {

    "EventCode": "0x400FE",

    "EventName": "PM_DATA_FROM_MEMORY",

tools/perf/pmu-events/arch/powerpc/power10/frontend.json

+10 −0
Original line number Diff line number Diff line
@@ -84,6 +84,11 @@ 
    "EventName": "PM_VECTOR_ST_CMPL",

    "BriefDescription": "Vector store instruction completed."

  },

  {

    "EventCode": "0x4D05E",

    "EventName": "PM_BR_CMPL",

    "BriefDescription": "A branch completed. All branches are included."

  },

  {

    "EventCode": "0x4E054",

    "EventName": "PM_DTLB_HIT_1G",
@@ -94,6 +99,11 @@ 
    "EventName": "PM_ITLB_MISS",

    "BriefDescription": "Instruction TLB reload (after a miss), all page sizes. Includes only demand misses."

  },

  {

    "EventCode": "0x00000048B4",

    "EventName": "PM_BR_TKN_UNCOND_FIN",

    "BriefDescription": "An unconditional branch finished. All unconditional branches are taken."

  },

  {

    "EventCode": "0x00000040B8",

    "EventName": "PM_PRED_BR_TKN_COND_DIR",

tools/perf/pmu-events/arch/powerpc/power10/locks.json

+10 −0
Original line number Diff line number Diff line
@@ -4,9 +4,19 @@ 
    "EventName": "PM_STCX_FAIL_FIN",

    "BriefDescription": "Conditional store instruction (STCX) failed. LARX and STCX are instructions used to acquire a lock."

  },

  {

    "EventCode": "0x2E014",

    "EventName": "PM_STCX_FIN",

    "BriefDescription": "Conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock."

  },

  {

    "EventCode": "0x4E050",

    "EventName": "PM_STCX_PASS_FIN",

    "BriefDescription": "Conditional store instruction (STCX) passed. LARX and STCX are instructions used to acquire a lock."

  },

  {

    "EventCode": "0x000000C8B8",

    "EventName": "PM_STCX_SUCCESS_CMPL",

    "BriefDescription": "STCX instructions that completed successfully. Specifically, counts only when a pass status is returned from the nest."

  }

]

tools/perf/pmu-events/arch/powerpc/power10/memory.json

+30 −0
Original line number Diff line number Diff line
@@ -69,6 +69,11 @@ 
    "EventName": "PM_XFER_FROM_SRC_PMC3",

    "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."

  },

  {

    "EventCode": "0x3F04A",

    "EventName": "PM_LSU_ST5_FIN",

    "BriefDescription": "LSU Finished an internal operation in ST2 port."

  },

  {

    "EventCode": "0x3C054",

    "EventName": "PM_DERAT_MISS_16M",
@@ -108,5 +113,30 @@ 
    "EventCode": "0x4C05A",

    "EventName": "PM_DTLB_MISS_1G",

    "BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."

  },

  {

    "EventCode": "0x000000F880",

    "EventName": "PM_SNOOP_TLBIE_CYC",

    "BriefDescription": "Cycles in which TLBIE snoops are executed in the LSU."

  },

  {

    "EventCode": "0x000000F084",

    "EventName": "PM_SNOOP_TLBIE_CACHE_WALK_CYC",

    "BriefDescription": "TLBIE snoop cycles in which the data cache is being walked."

  },

  {

    "EventCode": "0x000000F884",

    "EventName": "PM_SNOOP_TLBIE_WAIT_ST_CYC",

    "BriefDescription": "TLBIE snoop cycles in which older stores are still draining."

  },

  {

    "EventCode": "0x000000F088",

    "EventName": "PM_SNOOP_TLBIE_WAIT_LD_CYC",

    "BriefDescription": "TLBIE snoop cycles in which older loads are still draining."

  },

  {

    "EventCode": "0x000000F08C",

    "EventName": "PM_SNOOP_TLBIE_WAIT_MMU_CYC",

    "BriefDescription": "TLBIE snoop cycles in which the Load-Store unit is waiting for the MMU to finish invalidation."

  }

]