Commit 106f68fc authored by Adam Ford's avatar Adam Ford Committed by Shawn Guo
Browse files

arm64: dts: imx8mp: Fix pgc_mlmix location 



The pgc_mlmix shows a power-domain@24, but the reg value is
IMX8MP_POWER_DOMAIN_MLMIX which is set to 4.

The stuff after the @ symbol should match the stuff referenced
by 'reg' so reorder the pgc_mlmix so it to appear as power-domain@4.

Fixes: 834464c8 ("arm64: dts: imx8mp: add mlmix power domain")
Fixes: 4bedc468 ("arm64: dts: imx8mp: Add NPU Node")
Signed-off-by: default avatarAdam Ford <aford173@gmail.com>
Reviewed-by: default avatarPeng Fan <peng.fan@nxp.com>
Reviewed-by: default avatarMarek Vasut <marex@denx.de>
Reviewed-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent ee39dbd9

arch/arm64/boot/dts/freescale/imx8mp.dtsi

+17 −17
Original line number Diff line number Diff line
@@ -789,6 +789,23 @@ pgc_usb2_phy: power-domain@3 { 
						reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;

					};



					pgc_mlmix: power-domain@4 {

						#power-domain-cells = <0>;

						reg = <IMX8MP_POWER_DOMAIN_MLMIX>;

						clocks = <&clk IMX8MP_CLK_ML_AXI>,

							 <&clk IMX8MP_CLK_ML_AHB>,

							 <&clk IMX8MP_CLK_NPU_ROOT>;

						assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,

								  <&clk IMX8MP_CLK_ML_AXI>,

								  <&clk IMX8MP_CLK_ML_AHB>;

						assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,

									 <&clk IMX8MP_SYS_PLL1_800M>,

									 <&clk IMX8MP_SYS_PLL1_800M>;

						assigned-clock-rates = <800000000>,

								       <800000000>,

								       <300000000>;

					};



					pgc_audio: power-domain@5 {

						#power-domain-cells = <0>;

						reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
@@ -900,23 +917,6 @@ pgc_vpu_vc8000e: power-domain@22 { 
						reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;

						clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;

					};



					pgc_mlmix: power-domain@24 {

						#power-domain-cells = <0>;

						reg = <IMX8MP_POWER_DOMAIN_MLMIX>;

						clocks = <&clk IMX8MP_CLK_ML_AXI>,

							 <&clk IMX8MP_CLK_ML_AHB>,

							 <&clk IMX8MP_CLK_NPU_ROOT>;

						assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,

								  <&clk IMX8MP_CLK_ML_AXI>,

								  <&clk IMX8MP_CLK_ML_AHB>;

						assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,

									 <&clk IMX8MP_SYS_PLL1_800M>,

									 <&clk IMX8MP_SYS_PLL1_800M>;

						assigned-clock-rates = <800000000>,

								       <800000000>,

								       <300000000>;

					};

				};

			};

		};