Commit 11fdf087 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/dt-bindings' 

- Add Qualcomm QCS615 to SM8150 DT binding (Ziyue Zhang)

- Add Qualcomm QCS8300 to SA8775p DT binding (Ziyue Zhang)

- Add '6' (64 GT/s, aka Gen6) as a legal value for the DT endpoint
  'max-link-speed' property (Hans Zhang)

- Drop TBU and ref clocks from Qualcomm SM8150 and SC8180x DT bindings
  (Konrad Dybcio)

- Convert amazon,al-alpine-v[23]-pcie, apm,xgene-pcie, axis,artpec6-pcie,
  marvell,armada-3700-pcie, st,spear1340-pcie to DT schema format (Rob
  Herring)

- Document 'link_down' reset in Qualcomm SA8775P DT binding (Ziyue Zhang)

* pci/dt-bindings:
  dt-bindings: PCI: qcom,pcie-sa8775p: Document 'link_down' reset
  dt-bindings: PCI: Remove 83xx-512x-pci.txt
  dt-bindings: PCI: Convert amazon,al-alpine-v[23]-pcie to DT schema
  dt-bindings: PCI: Convert marvell,armada-3700-pcie to DT schema
  dt-bindings: PCI: Convert apm,xgene-pcie to DT schema
  dt-bindings: PCI: Convert axis,artpec6-pcie to DT schema
  dt-bindings: PCI: Convert st,spear1340-pcie to DT schema
  dt-bindings: PCI: qcom,pcie-sm8150: Drop unrelated clocks from PCIe hosts
  dt-bindings: PCI: qcom,pcie-sc8180x: Drop unrelated clocks from PCIe hosts
  dt-bindings: PCI: pci-ep: Extend max-link-speed to PCIe Gen5/Gen6
  dt-bindings: PCI: qcom,pcie-sa8775p: Document QCS8300
  dt-bindings: PCI: qcom,pcie-sm8150: Document QCS615
parents 29ccb7b9 fbcbd66f

Documentation/devicetree/bindings/pci/83xx-512x-pci.txt

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* Freescale 83xx and 512x PCI bridges



Freescale 83xx and 512x SOCs include the same PCI bridge core.



83xx/512x specific notes:

- reg: should contain two address length tuples

    The first is for the internal PCI bridge registers

    The second is for the PCI config space access registers



Example (MPC8313ERDB)

	pci0: pci@e0008500 {

		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;

		interrupt-map = <

				/* IDSEL 0x0E -mini PCI */

				 0x7000 0x0 0x0 0x1 &ipic 18 0x8

				 0x7000 0x0 0x0 0x2 &ipic 18 0x8

				 0x7000 0x0 0x0 0x3 &ipic 18 0x8

				 0x7000 0x0 0x0 0x4 &ipic 18 0x8



				/* IDSEL 0x0F - PCI slot */

				 0x7800 0x0 0x0 0x1 &ipic 17 0x8

				 0x7800 0x0 0x0 0x2 &ipic 18 0x8

				 0x7800 0x0 0x0 0x3 &ipic 17 0x8

				 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;

		interrupt-parent = <&ipic>;

		interrupts = <66 0x8>;

		bus-range = <0x0 0x0>;

		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000

			  0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000

			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;

		clock-frequency = <66666666>;

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <0xe0008500 0x100		/* internal registers */

		       0xe0008300 0x8>;		/* config space access registers */

		compatible = "fsl,mpc8349-pci";

		device_type = "pci";

	};

Documentation/devicetree/bindings/pci/aardvark-pci.txt

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Aardvark PCIe controller



This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.



The Device Tree node describing an Aardvark PCIe controller must

contain the following properties:



 - compatible: Should be "marvell,armada-3700-pcie"

 - reg: range of registers for the PCIe controller

 - interrupts: the interrupt line of the PCIe controller

 - #address-cells: set to <3>

 - #size-cells: set to <2>

 - device_type: set to "pci"

 - ranges: ranges for the PCI memory and I/O regions

 - #interrupt-cells: set to <1>

 - msi-controller: indicates that the PCIe controller can itself

   handle MSI interrupts

 - msi-parent: pointer to the MSI controller to be used

 - interrupt-map-mask and interrupt-map: standard PCI properties to

   define the mapping of the PCIe interface to interrupt numbers.

 - bus-range: PCI bus numbers covered

 - phys: the PCIe PHY handle

 - max-link-speed: see pci.txt

 - reset-gpios: see pci.txt



In addition, the Device Tree describing an Aardvark PCIe controller

must include a sub-node that describes the legacy interrupt controller

built into the PCIe controller. This sub-node must have the following

properties:



 - interrupt-controller

 - #interrupt-cells: set to <1>



Example:



	pcie0: pcie@d0070000 {

		compatible = "marvell,armada-3700-pcie";

		device_type = "pci";

		reg = <0 0xd0070000 0 0x20000>;

		#address-cells = <3>;

		#size-cells = <2>;

		bus-range = <0x00 0xff>;

		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;

		#interrupt-cells = <1>;

		msi-controller;

		msi-parent = <&pcie0>;

		ranges = <0x82000000 0 0xe8000000   0 0xe8000000 0 0x1000000 /* Port 0 MEM */

			  0x81000000 0 0xe9000000   0 0xe9000000 0 0x10000>; /* Port 0 IO*/

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &pcie_intc 0>,

				<0 0 0 2 &pcie_intc 1>,

				<0 0 0 3 &pcie_intc 2>,

				<0 0 0 4 &pcie_intc 3>;

		phys = <&comphy1 0>;

		pcie_intc: interrupt-controller {

			interrupt-controller;

			#interrupt-cells = <1>;

		};

	};

Documentation/devicetree/bindings/pci/amazon,al-alpine-v3-pcie.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/amazon,al-alpine-v3-pcie.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amazon Annapurna Labs Alpine v3 PCIe Host Bridge



maintainers:

  - Jonathan Chocron <jonnyc@amazon.com>



description:

  Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys

  DesignWare PCI controller.



allOf:

  - $ref: snps,dw-pcie.yaml#



properties:

  compatible:

    enum:

      - amazon,al-alpine-v2-pcie

      - amazon,al-alpine-v3-pcie



  reg:

    items:

      - description: PCIe ECAM space

      - description: AL proprietary registers

      - description: Designware PCIe registers



  reg-names:

    items:

      - const: config

      - const: controller

      - const: dbi



  interrupts:

    maxItems: 1



unevaluatedProperties: false



required:

  - compatible

  - reg

  - reg-names



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    bus {

        #address-cells = <2>;

        #size-cells = <2>;



        pcie@fb600000 {

            compatible = "amazon,al-alpine-v3-pcie";

            reg = <0x0 0xfb600000 0x0 0x00100000

                  0x0 0xfd800000 0x0 0x00010000

                  0x0 0xfd810000 0x0 0x00001000>;

            reg-names = "config", "controller", "dbi";

            bus-range = <0 255>;

            device_type = "pci";

            #address-cells = <3>;

            #size-cells = <2>;

            #interrupt-cells = <1>;

            interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-map-mask = <0x00 0 0 7>;

            interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */

            ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>;

        };

    };

Documentation/devicetree/bindings/pci/apm,xgene-pcie.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/apm,xgene-pcie.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: AppliedMicro X-Gene PCIe interface



maintainers:

  - Toan Le <toan@os.amperecomputing.com>



allOf:

  - $ref: /schemas/pci/pci-host-bridge.yaml#



properties:

  compatible:

    oneOf:

      - items:

          - const: apm,xgene-storm-pcie

          - const: apm,xgene-pcie

      - items:

          - const: apm,xgene-pcie



  reg:

    items:

      - description: Controller configuration registers

      - description: PCI configuration space registers



  reg-names:

    items:

      - const: csr

      - const: cfg



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: pcie



  dma-coherent: true



  msi-parent:

    maxItems: 1



required:

  - compatible

  - reg

  - reg-names

  - '#interrupt-cells'

  - interrupt-map-mask

  - interrupt-map

  - clocks



unevaluatedProperties: false



examples:

  - |

    bus {

        #address-cells = <2>;

        #size-cells = <2>;



        pcie@1f2b0000 {

            compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";

            device_type = "pci";

            #interrupt-cells = <1>;

            #size-cells = <2>;

            #address-cells = <3>;

            reg = <0x00 0x1f2b0000 0x0 0x00010000>, /* Controller registers */

                  <0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */

            reg-names = "csr", "cfg";

            ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000>, /* io */

                    <0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */

            dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000>,

                        <0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;

            interrupt-map-mask = <0x0 0x0 0x0 0x7>;

            interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1>,

                            <0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1>,

                            <0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1>,

                            <0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;

            dma-coherent;

            clocks = <&pcie0clk 0>;

        };

    };

Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt

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* Axis ARTPEC-6 PCIe interface



This PCIe host controller is based on the Synopsys DesignWare PCIe IP

and thus inherits all the common properties defined in snps,dw-pcie.yaml.



Required properties:

- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;

	      "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;

	      "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;

	      "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;

- reg: base addresses and lengths of the PCIe controller (DBI),

	the PHY controller, and configuration address space.

- reg-names: Must include the following entries:

	- "dbi"

	- "phy"

	- "config"

- interrupts: A list of interrupt outputs of the controller. Must contain an

  entry for each entry in the interrupt-names property.

- interrupt-names: Must include the following entries:

	- "msi": The interrupt that is asserted when an MSI is received

- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller,

	used to enable and control the Synopsys IP.



Example:



	pcie@f8050000 {

		compatible = "axis,artpec6-pcie", "snps,dw-pcie";

		reg = <0xf8050000 0x2000

		       0xf8040000 0x1000

		       0xc0000000 0x2000>;

		reg-names = "dbi", "phy", "config";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

			  /* downstream I/O */

		ranges = <0x81000000 0 0 0xc0002000 0 0x00010000

			  /* non-prefetchable memory */

			  0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;

		num-lanes = <2>;

		bus-range = <0x00 0xff>;

		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "msi";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0x7>;

		interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,

		                <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,

		                <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,

		                <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;

		axis,syscon-pcie = <&syscon>;

	};