Commit 12b6c62c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2025-05-17' of https://gitlab.freedesktop.org/drm/kernel 

Pull drm fixes from Dave Airlie:
 "Weekly drm fixes, I'll be honest and say I think this is larger than
  I'd prefer at this point, the main blow out point is that xe has two
  larger fixes.

  One is a fix for active context utilisation reporting, it's for a
  reported regression and will end up in stable anyways, so I don't see
  any point in holding it up.

  The second is a fix for mixed cpu/gpu atomics, which are currently
  broken, but are also not something your average desktop/laptop user is
  going to hit in normal operation, and having them fixed now is better
  than threading them through stable later.

  Other than those, it's mostly the usual, a bunch of amdgpu randoms and
  a few other minor fixes.

  dma-buf:
   - Avoid memory reordering in fence handling

  meson:
   - Avoid integer overflow in mode-clock calculations

  panel-mipi-dbi:
   - Fix output with drm_client_setup_with_fourcc()

  amdgpu:
   - Fix CSA unmap
   - Fix MALL size reporting on GFX11.5
   - AUX fix
   - DCN 3.5 fix
   - VRR fix
   - DP MST fix
   - DML 2.1 fixes
   - Silence DP AUX spam
   - DCN 4.0.1 cursor fix
   - VCN 4.0.5 fix

  ivpu:
   - Fix buffer size in debugfs code

  gpuvm:
   - Add timeslicing and allocation restriction for SVM

  xe:
   - Fix shrinker debugfs name
   - Add HW workaround to Xe2
   - Fix SVM when mixing GPU and CPU atomics
   - Fix per client engine utilization due to active contexts not saving
     timestamp with lite restore enabled"

* tag 'drm-fixes-2025-05-17' of https://gitlab.freedesktop.org/drm/kernel: (24 commits)
  drm/xe: Add WA BB to capture active context utilization
  drm/xe: Save the gt pointer in lrc and drop the tile
  drm/xe: Save CTX_TIMESTAMP mmio value instead of LRC value
  drm/xe: Timeslice GPU on atomic SVM fault
  drm/gpusvm: Add timeslicing support to GPU SVM
  drm/xe: Strict migration policy for atomic SVM faults
  drm/gpusvm: Introduce devmem_only flag for allocation
  drm/xe/xe2hpg: Add Wa_22021007897
  drm/amdgpu: read back register after written for VCN v4.0.5
  Revert "drm/amd/display: Hardware cursor changes color when switched to software cursor"
  dma-buf: insert memory barrier before updating num_fences
  drm/xe: Fix the gem shrinker name
  drm/amd/display: Avoid flooding unnecessary info messages
  drm/amd/display: Fix null check of pipe_ctx->plane_state for update_dchubp_dpp
  drm/amd/display: check stream id dml21 wrapper to get plane_id
  drm/amd/display: fix link_set_dpms_off multi-display MST corner case
  drm/amd/display: Defer BW-optimization-blocked DRR adjustments
  Revert: "drm/amd/display: Enable urgent latency adjustment on DCN35"
  drm/amd/display: Correct the reply value when AUX write incomplete
  drm/amdgpu: fix incorrect MALL size for GFX1151
  ...
parents 450d2f6e c81dbc49

drivers/accel/ivpu/ivpu_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -455,7 +455,7 @@ priority_bands_fops_write(struct file *file, const char __user *user_buf, size_t 
	if (ret < 0)

		return ret;



	buf[size] = '\0';

	buf[ret] = '\0';

	ret = sscanf(buf, "%u %u %u %u", &band, &grace_period, &process_grace_period,

		     &process_quantum);

	if (ret != 4)

drivers/dma-buf/dma-resv.c

+3 −2
Original line number Diff line number Diff line
@@ -320,8 +320,9 @@ void dma_resv_add_fence(struct dma_resv *obj, struct dma_fence *fence, 
	count++;



	dma_resv_list_set(fobj, i, fence, usage);

	/* pointer update must be visible before we extend the num_fences */

	smp_store_mb(fobj->num_fences, count);

	/* fence update must be visible before we extend the num_fences */

	smp_wmb();

	fobj->num_fences = count;

}

EXPORT_SYMBOL(dma_resv_add_fence);

drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c

+1 −1
Original line number Diff line number Diff line
@@ -109,7 +109,7 @@ int amdgpu_unmap_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm, 
	struct drm_exec exec;

	int r;



	drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);

	drm_exec_init(&exec, 0, 0);

	drm_exec_until_all_locked(&exec) {

		r = amdgpu_vm_lock_pd(vm, &exec, 0);

		if (likely(!r))

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

+12 −0
Original line number Diff line number Diff line
@@ -752,6 +752,18 @@ static int gmc_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 
	adev->gmc.vram_type = vram_type;

	adev->gmc.vram_vendor = vram_vendor;



	/* The mall_size is already calculated as mall_size_per_umc * num_umc.

	 * However, for gfx1151, which features a 2-to-1 UMC mapping,

	 * the result must be multiplied by 2 to determine the actual mall size.

	 */

	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {

	case IP_VERSION(11, 5, 1):

		adev->gmc.mall_size *= 2;

		break;

	default:

		break;

	}



	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {

	case IP_VERSION(11, 0, 0):

	case IP_VERSION(11, 0, 1):

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

+8 −0
Original line number Diff line number Diff line
@@ -1023,6 +1023,10 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 
			ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |

			VCN_RB1_DB_CTRL__EN_MASK);



	/* Keeping one read-back to ensure all register writes are done, otherwise

	 * it may introduce race conditions */

	RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL);



	return 0;

}
@@ -1205,6 +1209,10 @@ static int vcn_v4_0_5_start(struct amdgpu_vcn_inst *vinst) 
	WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);

	fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);



	/* Keeping one read-back to ensure all register writes are done, otherwise

	 * it may introduce race conditions */

	RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);



	return 0;

}