Commit 12c069e0 authored by Nicolas Frattaroli's avatar Nicolas Frattaroli Committed by Liviu Dudau
Browse files

dt-bindings: gpu: mali-valhall-csf: add mediatek,mt8196-mali variant 



The Mali-based GPU on the MediaTek MT8196 SoC uses a separate MCU to
control the power and frequency of the GPU. This is modelled as a power
domain and clock provider.

It lets us omit the OPP tables from the device tree, as those can now be
enumerated at runtime from the MCU.

Add the necessary schema logic to handle what this SoC expects in terms
of clocks and power-domains.

Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarLiviu Dudau <liviu.dudau@arm.com>
Signed-off-by: default avatarNicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://patch.msgid.link/20251017-mt8196-gpufreq-v8-1-98fc1cc566a1@collabora.com


Signed-off-by: default avatarLiviu Dudau <liviu.dudau@arm.com>
parent 67934f24

Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml

+36 −1
Original line number Diff line number Diff line
@@ -46,7 +46,9 @@ properties: 
    minItems: 1

    items:

      - const: core

      - const: coregroup

      - enum:

          - coregroup

          - stacks

      - const: stacks



  mali-supply: true
@@ -111,6 +113,27 @@ allOf: 
        power-domain-names: false

      required:

        - mali-supply

  - if:

      properties:

        compatible:

          contains:

            const: mediatek,mt8196-mali

    then:

      properties:

        mali-supply: false

        sram-supply: false

        operating-points-v2: false

        power-domains:

          maxItems: 1

        power-domain-names: false

        clocks:

          maxItems: 2

        clock-names:

          items:

            - const: core

            - const: stacks

      required:

        - power-domains



examples:

  - |
@@ -146,5 +169,17 @@ examples: 
            };

        };

    };

  - |

    gpu@48000000 {

        compatible = "mediatek,mt8196-mali", "arm,mali-valhall-csf";

        reg = <0x48000000 0x480000>;

        clocks = <&gpufreq 0>, <&gpufreq 1>;

        clock-names = "core", "stacks";

        interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH 0>,

                     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH 0>,

                     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>;

        interrupt-names = "job", "mmu", "gpu";

        power-domains = <&gpufreq>;

    };



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