Commit 140bb9e9 authored by Miquel Raynal's avatar Miquel Raynal
Browse files

mtd: spinand: winbond: Rename DTR variants 



So far all the chips supported in the driver apparently have support for
the same kind of operation (typically, single, dual and quad). The
future introduction of W35N chips will change that as these chips only
support single and octal modes. Let's rename the variants accordingly to
make these future additions more understandable.

Acked-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
parent 51b252cc

drivers/mtd/nand/spi/winbond.c

+3 −3
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ 
 * "X4" in the core is equivalent to "quad output" in the datasheets.

 */



static SPINAND_OP_VARIANTS(read_cache_dtr_variants,

static SPINAND_OP_VARIANTS(read_cache_dual_quad_dtr_variants,

		SPINAND_PAGE_READ_FROM_CACHE_1S_4D_4D_OP(0, 8, NULL, 0, 80 * HZ_PER_MHZ),

		SPINAND_PAGE_READ_FROM_CACHE_1S_1D_4D_OP(0, 2, NULL, 0, 80 * HZ_PER_MHZ),

		SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(0, 2, NULL, 0),
@@ -213,7 +213,7 @@ static const struct spinand_info winbond_spinand_table[] = { 
		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbc, 0x21),

		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),

		     NAND_ECCREQ(1, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_dtr_variants,

		     SPINAND_INFO_OP_VARIANTS(&read_cache_dual_quad_dtr_variants,

					      &write_cache_variants,

					      &update_cache_variants),

		     0,
@@ -242,7 +242,7 @@ static const struct spinand_info winbond_spinand_table[] = { 
		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbf, 0x22),

		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 2, 1),

		     NAND_ECCREQ(1, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_dtr_variants,

		     SPINAND_INFO_OP_VARIANTS(&read_cache_dual_quad_dtr_variants,

					      &write_cache_variants,

					      &update_cache_variants),

		     0,