Commit 144dfe40 authored by Quan Zhou's avatar Quan Zhou Committed by Anup Patel
Browse files

KVM: riscv: selftests: Add Svvptc/Zabha/Ziccrse exts to get-reg-list test 



The KVM RISC-V allows Svvptc/Zabha/Ziccrse extensions for Guest/VM
so add them to get-reg-list test.

Signed-off-by: default avatarQuan Zhou <zhouquan@iscas.ac.cn>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/35163f0443993a942e0a021c6006bc5d2f0f5d5f.1732854096.git.zhouquan@iscas.ac.cn


Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 79be257b

tools/testing/selftests/kvm/riscv/get-reg-list.c

+12 −0
Original line number Diff line number Diff line
@@ -52,6 +52,8 @@ bool filter_reg(__u64 reg) 
	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVVPTC:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZABHA:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZACAS:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAWRS:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBA:
@@ -71,6 +73,7 @@ bool filter_reg(__u64 reg) 
	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICCRSE:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICOND:

	case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICSR:
@@ -430,6 +433,8 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) 
		KVM_ISA_EXT_ARR(SVINVAL),

		KVM_ISA_EXT_ARR(SVNAPOT),

		KVM_ISA_EXT_ARR(SVPBMT),

		KVM_ISA_EXT_ARR(SVVPTC),

		KVM_ISA_EXT_ARR(ZABHA),

		KVM_ISA_EXT_ARR(ZACAS),

		KVM_ISA_EXT_ARR(ZAWRS),

		KVM_ISA_EXT_ARR(ZBA),
@@ -449,6 +454,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) 
		KVM_ISA_EXT_ARR(ZFHMIN),

		KVM_ISA_EXT_ARR(ZICBOM),

		KVM_ISA_EXT_ARR(ZICBOZ),

		KVM_ISA_EXT_ARR(ZICCRSE),

		KVM_ISA_EXT_ARR(ZICNTR),

		KVM_ISA_EXT_ARR(ZICOND),

		KVM_ISA_EXT_ARR(ZICSR),
@@ -967,6 +973,8 @@ KVM_ISA_EXT_SIMPLE_CONFIG(svadu, SVADU); 
KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL);

KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT);

KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT);

KVM_ISA_EXT_SIMPLE_CONFIG(svvptc, SVVPTC);

KVM_ISA_EXT_SIMPLE_CONFIG(zabha, ZABHA);

KVM_ISA_EXT_SIMPLE_CONFIG(zacas, ZACAS);

KVM_ISA_EXT_SIMPLE_CONFIG(zawrs, ZAWRS);

KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA);
@@ -986,6 +994,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH); 
KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN);

KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);

KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);

KVM_ISA_EXT_SIMPLE_CONFIG(ziccrse, ZICCRSE);

KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR);

KVM_ISA_EXT_SIMPLE_CONFIG(zicond, ZICOND);

KVM_ISA_EXT_SIMPLE_CONFIG(zicsr, ZICSR);
@@ -1035,6 +1044,8 @@ struct vcpu_reg_list *vcpu_configs[] = { 
	&config_svinval,

	&config_svnapot,

	&config_svpbmt,

	&config_svvptc,

	&config_zabha,

	&config_zacas,

	&config_zawrs,

	&config_zba,
@@ -1054,6 +1065,7 @@ struct vcpu_reg_list *vcpu_configs[] = { 
	&config_zfhmin,

	&config_zicbom,

	&config_zicboz,

	&config_ziccrse,

	&config_zicntr,

	&config_zicond,

	&config_zicsr,