Commit 145916f6 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-meson-v6.8-1' of https://github.com/BayLibre/clk-meson into clk-amlogic 

Pull Amlogic clk driver updates from Jerome Brunet:

 - Add DSI clocks on Amlogic g12/sm1
 - Add CSI and ISP clocks on Amlogic g12/sm1

* tag 'clk-meson-v6.8-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: g12a: add CSI & ISP gates clocks
  clk: meson: g12a: add MIPI ISP clocks
  dt-bindings: clock: g12a-clkc: add MIPI ISP & CSI PHY clock ids
  clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocks
  dt-bindings: clk: g12a-clkc: add CTS_ENCL clock ids
parents b85ea95d 5205628a

drivers/clk/meson/g12a.c

+115 −0
Original line number Diff line number Diff line
@@ -3549,6 +3549,22 @@ static struct clk_regmap g12a_cts_encp_sel = { 
	},

};



static struct clk_regmap g12a_cts_encl_sel = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_VIID_CLK_DIV,

		.mask = 0xf,

		.shift = 12,

		.table = mux_table_cts_sel,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cts_encl_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_hws = g12a_cts_parent_hws,

		.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),

		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,

	},

};



static struct clk_regmap g12a_cts_vdac_sel = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_VIID_CLK_DIV,
@@ -3628,6 +3644,22 @@ static struct clk_regmap g12a_cts_encp = { 
	},

};



static struct clk_regmap g12a_cts_encl = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_VID_CLK_CNTL2,

		.bit_idx = 3,

	},

	.hw.init = &(struct clk_init_data) {

		.name = "cts_encl",

		.ops = &clk_regmap_gate_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_cts_encl_sel.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,

	},

};



static struct clk_regmap g12a_cts_vdac = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_VID_CLK_CNTL2,
@@ -3722,6 +3754,66 @@ static struct clk_regmap g12a_mipi_dsi_pxclk = { 
	},

};



/* MIPI ISP Clocks */



static const struct clk_parent_data g12b_mipi_isp_parent_data[] = {

	{ .fw_name = "xtal", },

	{ .hw = &g12a_gp0_pll.hw },

	{ .hw = &g12a_hifi_pll.hw },

	{ .hw = &g12a_fclk_div2p5.hw },

	{ .hw = &g12a_fclk_div3.hw },

	{ .hw = &g12a_fclk_div4.hw },

	{ .hw = &g12a_fclk_div5.hw },

	{ .hw = &g12a_fclk_div7.hw },

};



static struct clk_regmap g12b_mipi_isp_sel = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_ISP_CLK_CNTL,

		.mask = 7,

		.shift = 9,

	},

	.hw.init = &(struct clk_init_data){

		.name = "mipi_isp_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_data = g12b_mipi_isp_parent_data,

		.num_parents = ARRAY_SIZE(g12b_mipi_isp_parent_data),

	},

};



static struct clk_regmap g12b_mipi_isp_div = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_ISP_CLK_CNTL,

		.shift = 0,

		.width = 7,

	},

	.hw.init = &(struct clk_init_data){

		.name = "mipi_isp_div",

		.ops = &clk_regmap_divider_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12b_mipi_isp_sel.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap g12b_mipi_isp = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_ISP_CLK_CNTL,

		.bit_idx = 8,

	},

	.hw.init = &(struct clk_init_data) {

		.name = "mipi_isp",

		.ops = &clk_regmap_gate_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12b_mipi_isp_div.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



/* HDMI Clocks */



static const struct clk_parent_data g12a_hdmi_parent_data[] = {
@@ -4214,9 +4306,12 @@ static MESON_GATE(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3); 
static MESON_GATE(g12a_htx_pclk,		HHI_GCLK_MPEG2,	4);

static MESON_GATE(g12a_bt656,			HHI_GCLK_MPEG2,	6);

static MESON_GATE(g12a_usb1_to_ddr,		HHI_GCLK_MPEG2,	8);

static MESON_GATE(g12b_mipi_isp_gate,		HHI_GCLK_MPEG2,	17);

static MESON_GATE(g12a_mmc_pclk,		HHI_GCLK_MPEG2,	11);

static MESON_GATE(g12a_uart2,			HHI_GCLK_MPEG2,	15);

static MESON_GATE(g12a_vpu_intr,		HHI_GCLK_MPEG2,	25);

static MESON_GATE(g12b_csi_phy1,		HHI_GCLK_MPEG2,	28);

static MESON_GATE(g12b_csi_phy0,		HHI_GCLK_MPEG2,	29);

static MESON_GATE(g12a_gic,			HHI_GCLK_MPEG2,	30);



static MESON_GATE(g12a_vclk2_venci0,		HHI_GCLK_OTHER,	1);
@@ -4407,10 +4502,12 @@ static struct clk_hw *g12a_hw_clks[] = { 
	[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,

	[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,

	[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,

	[CLKID_CTS_ENCL_SEL]		= &g12a_cts_encl_sel.hw,

	[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,

	[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,

	[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,

	[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,

	[CLKID_CTS_ENCL]		= &g12a_cts_encl.hw,

	[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,

	[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,

	[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
@@ -4632,10 +4729,12 @@ static struct clk_hw *g12b_hw_clks[] = { 
	[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,

	[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,

	[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,

	[CLKID_CTS_ENCL_SEL]		= &g12a_cts_encl_sel.hw,

	[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,

	[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,

	[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,

	[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,

	[CLKID_CTS_ENCL]		= &g12a_cts_encl.hw,

	[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,

	[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,

	[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
@@ -4729,6 +4828,12 @@ static struct clk_hw *g12b_hw_clks[] = { 
	[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,

	[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,

	[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,

	[CLKID_MIPI_ISP_SEL]		= &g12b_mipi_isp_sel.hw,

	[CLKID_MIPI_ISP_DIV]		= &g12b_mipi_isp_div.hw,

	[CLKID_MIPI_ISP]		= &g12b_mipi_isp.hw,

	[CLKID_MIPI_ISP_GATE]		= &g12b_mipi_isp_gate.hw,

	[CLKID_MIPI_ISP_CSI_PHY0]	= &g12b_csi_phy0.hw,

	[CLKID_MIPI_ISP_CSI_PHY1]	= &g12b_csi_phy1.hw,

};



static struct clk_hw *sm1_hw_clks[] = {
@@ -4892,10 +4997,12 @@ static struct clk_hw *sm1_hw_clks[] = { 
	[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,

	[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,

	[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,

	[CLKID_CTS_ENCL_SEL]		= &g12a_cts_encl_sel.hw,

	[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,

	[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,

	[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,

	[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,

	[CLKID_CTS_ENCL]		= &g12a_cts_encl.hw,

	[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,

	[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,

	[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
@@ -5123,10 +5230,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { 
	&g12a_vclk2_div12_en,

	&g12a_cts_enci_sel,

	&g12a_cts_encp_sel,

	&g12a_cts_encl_sel,

	&g12a_cts_vdac_sel,

	&g12a_hdmi_tx_sel,

	&g12a_cts_enci,

	&g12a_cts_encp,

	&g12a_cts_encl,

	&g12a_cts_vdac,

	&g12a_hdmi_tx,

	&g12a_hdmi_sel,
@@ -5221,6 +5330,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { 
	&g12a_mipi_dsi_pxclk_sel,

	&g12a_mipi_dsi_pxclk_div,

	&g12a_mipi_dsi_pxclk,

	&g12b_mipi_isp_sel,

	&g12b_mipi_isp_div,

	&g12b_mipi_isp,

	&g12b_mipi_isp_gate,

	&g12b_csi_phy1,

	&g12b_csi_phy0,

};



static const struct reg_sequence g12a_init_regs[] = {

drivers/clk/meson/g12a.h

+1 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ 
#define HHI_MALI_CLK_CNTL		0x1b0

#define HHI_VPU_CLKC_CNTL		0x1b4

#define HHI_VPU_CLK_CNTL		0x1bC

#define HHI_ISP_CLK_CNTL		0x1C0

#define HHI_NNA_CLK_CNTL		0x1C8

#define HHI_HDMI_CLK_CNTL		0x1CC

#define HHI_VDEC_CLK_CNTL		0x1E0

include/dt-bindings/clock/g12a-clkc.h

+8 −0
Original line number Diff line number Diff line
@@ -279,5 +279,13 @@ 
#define CLKID_MIPI_DSI_PXCLK_DIV		268

#define CLKID_MIPI_DSI_PXCLK_SEL		269

#define CLKID_MIPI_DSI_PXCLK			270

#define CLKID_CTS_ENCL				271

#define CLKID_CTS_ENCL_SEL			272

#define CLKID_MIPI_ISP_DIV			273

#define CLKID_MIPI_ISP_SEL			274

#define CLKID_MIPI_ISP				275

#define CLKID_MIPI_ISP_GATE			276

#define CLKID_MIPI_ISP_CSI_PHY0			277

#define CLKID_MIPI_ISP_CSI_PHY1			278



#endif /* __G12A_CLKC_H */