Commit 16893dd2 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2025-02-24' of... 

Merge tag 'drm-intel-next-2025-02-24' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-next

drm/i915 feature pull for v6.15:

Features and functionality:
- Enable DP 128b/132b SST DSC (Jani, Imre)
- Allow DSB to perform commits when VRR is enabled (Ville)
- Compute HDMI PLLs for SNPS/C10 PHYs for rates not in fixed tables (Ankit)
- Allow DSB usage when PSR is enabled on LNL+ (Jouni)
- Enable Panel Replay mode change without full modeset (Jouni)
- Enable async flips with compressed buffers on ICL+ (Ville)
- Support luminance based brightness control via DPCD for eDP (Suraj)
- Enable VRR enable/disable without full modeset (Mitul, Ankit)
- Add debugfs facility for force testing HDCP 1.4 (Suraj)
- Add scaler tracepoints, improve plane tracepoints (Ville)
- Improve DMC wakelock debugging facilities (Gustavo)
- Allow GuC SLPC default strategies on MTL+ for performance (Rodrigo)
- Provide more information on display faults (Ville)

Refactoring and cleanups:
- Continue conversions to struct intel_display (Ville, Jani, Suraj, Imre)
- Joiner and Y plane reorganization (Ville)
- Move HDCP debugfs to intel_hdcp.c (Jani)
- Clean up and unify LSPCON interfaces (Jani)
- Move code out of intel_display.c to reduce its size (Ville)
- Clean up and simplify DDI port enabling/disabling (Imre)
- Make LPT LP a dedicated PCH type, refactor (Jani)
- Simplify DSC range BPG offset calculation (Ankit)
- Scaler cleanups (Ville)
- Remove unused code from GVT (David Alan Gilbert)
- Improve plane debugging (Ville)
- DSB and VRR refactoring (Ville)

Fixes:
- Check if vblank is sufficient for DSC prefill and scaler (Mitul)
- Fix Mesa clear color alignment regression (Ville)
- Add missing TC DP PHY lane stagger delay (Imre)
- Fix DSB + VRR usage for PTL+ (Ville)
- Improve robustness of display VT-d workarounds (Ville)
- Fix platforms for dbuf tracker state service programming (Ravi)
- Fix DMC wakelock support conditions (Gustavo)
- Amend DMC wakelock register ranges (Gustavo)
- Disable the Common Primary Timing Generator (CMTG) (Gustavo)
- Enable C20 PHY SSC (Suraj)
- Add workaround for DKL PHY DP mode write (Nemesa)
- Fix build warnings on clamp() usage (Guenter Roeck, Ankit)
- Fix error handling while adding a connector (Imre)
- Avoid full modeset at probe on vblank delay mismatches (Ville)
- Fix encoder HDMI check for HDCP line rekeying (Suraj)
- Fix HDCP repeater authentication during topology change (Suraj)
- Handle display PHY power state reset for power savings (Mika)
- Fix typos all over the place (Nitin)
- Update HDMI TMDS C20 parameters for various platforms (Dnyaneshwar)
- Guarantee a minimum hblank time for 128b/132b and 8b/10b MST (Arun, Imre)
- Do not hardcode LSPCON settle timeout (Giedrius Statkevičius)

Xe driver changes:
- Re-use display vmas when possible (Maarten)
- Remove double pageflip (Maarten)
- Enable DP tunneling (Imre)
- Separate i915 and xe tracepoints (Ville)

DRM core changes:
- Increase DPCD eDP display control CAP size to 5 bytes (Suraj)
- Add DPCD eDP version 1.5 definition (Suraj)
- Add timeout parameter to drm_lspcon_set_mode() (Giedrius Statkevičius)

Merges:
- Backmerge drm-next (Jani)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87h64j7b7n.fsf@intel.com
parents 425b8481 5b99dd12

MAINTAINERS

+1 −1
Original line number Diff line number Diff line
@@ -11635,7 +11635,7 @@ F: drivers/gpio/gpio-tangier.c 
F:	drivers/gpio/gpio-tangier.h









INTEL GVT-g DRIVERS (Intel GPU Virtualization)









M:	Zhenyu Wang <zhenyuw@linux.intel.com>









M:	Zhenyu Wang <zhenyuw.linux@gmail.com>









M:	Zhi Wang <zhi.wang.linux@gmail.com>









L:	intel-gvt-dev@lists.freedesktop.org









L:	intel-gfx@lists.freedesktop.org
































drivers/gpu/drm/display/drm_dp_dual_mode_helper.c



+2
−2






























Original line number
Diff line number
Diff line







@@ -486,16 +486,16 @@ EXPORT_SYMBOL(drm_lspcon_get_mode);







 * @dev: &drm_device to use









 * @adapter: I2C-over-aux adapter









 * @mode: required mode of operation









 * @time_out: LSPCON mode change settle timeout









 *









 * Returns:









 * 0 on success, -error on failure/timeout









 */









int drm_lspcon_set_mode(const struct drm_device *dev, struct i2c_adapter *adapter,









			enum drm_lspcon_mode mode)









			enum drm_lspcon_mode mode, int time_out)









{









	u8 data = 0;









	int ret;









	int time_out = 200;









	enum drm_lspcon_mode current_mode;



















	if (mode == DRM_LSPCON_MODE_PCON)
































drivers/gpu/drm/i915/Makefile



+2
−0






























Original line number
Diff line number
Diff line







@@ -231,6 +231,7 @@ i915-y += \







	display/intel_bo.o \









	display/intel_bw.o \









	display/intel_cdclk.o \









	display/intel_cmtg.o \









	display/intel_color.o \









	display/intel_combo_phy.o \









	display/intel_connector.o \








@@ -346,6 +347,7 @@ i915-y += \







	display/intel_pps.o \









	display/intel_qp_tables.o \









	display/intel_sdvo.o \









	display/intel_snps_hdmi_pll.o \









	display/intel_snps_phy.o \









	display/intel_tv.o \









	display/intel_vdsc.o \
































drivers/gpu/drm/i915/display/dvo_ns2501.c



+1
−1






























Original line number
Diff line number
Diff line







@@ -517,7 +517,7 @@ static enum drm_connector_status ns2501_detect(struct intel_dvo_device *dvo)







	 * Even if not, the detection bit of the 2501 is unreliable as









	 * it only works for some display types.









	 * It is even more unreliable as the PLL must be active for









	 * allowing reading from the chiop.









	 * allowing reading from the chip.









	 */









	return connector_status_connected;









}
































drivers/gpu/drm/i915/display/g4x_dp.c



+53
−59






























Original line number
Diff line number
Diff line







@@ -51,28 +51,29 @@ static const struct dpll chv_dpll[] = {







	{ .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },









};



















const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)









const struct dpll *vlv_get_dpll(struct intel_display *display)









{









	return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0];









	return display->platform.cherryview ? &chv_dpll[0] : &vlv_dpll[0];









}



















static void g4x_dp_set_clock(struct intel_encoder *encoder,









			     struct intel_crtc_state *pipe_config)









{









	struct intel_display *display = to_intel_display(encoder);









	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);









	const struct dpll *divisor = NULL;









	int i, count = 0;



















	if (IS_G4X(dev_priv)) {









	if (display->platform.g4x) {









		divisor = g4x_dpll;









		count = ARRAY_SIZE(g4x_dpll);









	} else if (HAS_PCH_SPLIT(dev_priv)) {









		divisor = pch_dpll;









		count = ARRAY_SIZE(pch_dpll);









	} else if (IS_CHERRYVIEW(dev_priv)) {









	} else if (display->platform.cherryview) {









		divisor = chv_dpll;









		count = ARRAY_SIZE(chv_dpll);









	} else if (IS_VALLEYVIEW(dev_priv)) {









	} else if (display->platform.valleyview) {









		divisor = vlv_dpll;









		count = ARRAY_SIZE(vlv_dpll);









	}








@@ -129,7 +130,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,

















	/* Split out the IBX/CPU vs CPT settings */



















	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {









	if (display->platform.ivybridge && port == PORT_A) {









		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)









			intel_dp->DP |= DP_SYNC_HS_HIGH;









		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)








@@ -148,7 +149,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,







			     pipe_config->enhanced_framing ?









			     TRANS_DP_ENH_FRAMING : 0);









	} else {









		if (IS_G4X(dev_priv) && pipe_config->limited_color_range)









		if (display->platform.g4x && pipe_config->limited_color_range)









			intel_dp->DP |= DP_COLOR_RANGE_16_235;



















		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)








@@ -160,7 +161,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,







		if (pipe_config->enhanced_framing)









			intel_dp->DP |= DP_ENHANCED_FRAMING;



















		if (IS_CHERRYVIEW(dev_priv))









		if (display->platform.cherryview)









			intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);









		else









			intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);








@@ -180,9 +181,8 @@ static void assert_dp_port(struct intel_dp *intel_dp, bool state)







}









#define assert_dp_port_disabled(d) assert_dp_port((d), false)



















static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)









static void assert_edp_pll(struct intel_display *display, bool state)









{









	struct intel_display *display = &dev_priv->display;









	bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE;



















	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,








@@ -197,11 +197,10 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,







{









	struct intel_display *display = to_intel_display(intel_dp);









	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);









	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);



















	assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);









	assert_transcoder_disabled(display, pipe_config->cpu_transcoder);









	assert_dp_port_disabled(intel_dp);









	assert_edp_pll_disabled(dev_priv);









	assert_edp_pll_disabled(display);



















	drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n",









		    pipe_config->port_clock);








@@ -223,8 +222,8 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,







	 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI









	 * 2. Program DP PLL enable









	 */









	if (IS_IRONLAKE(dev_priv))









		intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);









	if (display->platform.ironlake)









		intel_wait_for_vblank_if_active(display, !crtc->pipe);



















	intel_dp->DP |= DP_PLL_ENABLE;


















@@ -237,12 +236,10 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp,







			    const struct intel_crtc_state *old_crtc_state)









{









	struct intel_display *display = to_intel_display(intel_dp);









	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);









	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);



















	assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);









	assert_transcoder_disabled(display, old_crtc_state->cpu_transcoder);









	assert_dp_port_disabled(intel_dp);









	assert_edp_pll_enabled(dev_priv);









	assert_edp_pll_enabled(display);



















	drm_dbg_kms(display->drm, "disabling eDP PLL\n");


















@@ -253,10 +250,9 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp,







	udelay(200);









}



















static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,









static bool cpt_dp_port_selected(struct intel_display *display,









				 enum port port, enum pipe *pipe)









{









	struct intel_display *display = &dev_priv->display;









	enum pipe p;



















	for_each_pipe(display, p) {








@@ -277,11 +273,11 @@ static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,







	return false;









}



















bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,









bool g4x_dp_port_enabled(struct intel_display *display,









			 i915_reg_t dp_reg, enum port port,









			 enum pipe *pipe)









{









	struct intel_display *display = &dev_priv->display;









	struct drm_i915_private *dev_priv = to_i915(display->drm);









	bool ret;









	u32 val;


















@@ -290,11 +286,11 @@ bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,







	ret = val & DP_PORT_EN;



















	/* asserts want to know the pipe even if the port is disabled */









	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)









	if (display->platform.ivybridge && port == PORT_A)









		*pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;









	else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)









		ret &= cpt_dp_port_selected(dev_priv, port, pipe);









	else if (IS_CHERRYVIEW(dev_priv))









		ret &= cpt_dp_port_selected(display, port, pipe);









	else if (display->platform.cherryview)









		*pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;









	else









		*pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;








@@ -305,20 +301,20 @@ bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,







static bool intel_dp_get_hw_state(struct intel_encoder *encoder,









				  enum pipe *pipe)









{









	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);









	struct intel_display *display = to_intel_display(encoder);









	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);









	intel_wakeref_t wakeref;









	bool ret;



















	wakeref = intel_display_power_get_if_enabled(dev_priv,









	wakeref = intel_display_power_get_if_enabled(display,









						     encoder->power_domain);









	if (!wakeref)









		return false;



















	ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,









	ret = g4x_dp_port_enabled(display, intel_dp->output_reg,









				  encoder->port, pipe);



















	intel_display_power_put(dev_priv, encoder->power_domain, wakeref);









	intel_display_power_put(display, encoder->power_domain, wakeref);



















	return ret;









}








@@ -390,7 +386,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,

















	pipe_config->hw.adjusted_mode.flags |= flags;



















	if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)









	if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235)









		pipe_config->limited_color_range = true;



















	pipe_config->lane_count =








@@ -432,7 +428,7 @@ intel_dp_link_down(struct intel_encoder *encoder,

















	drm_dbg_kms(display->drm, "\n");



















	if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||









	if ((display->platform.ivybridge && port == PORT_A) ||









	    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {









		intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;









		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;








@@ -457,8 +453,8 @@ intel_dp_link_down(struct intel_encoder *encoder,







		 * We get CPU/PCH FIFO underruns on the other pipe when









		 * doing the workaround. Sweep them under the rug.









		 */









		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);









		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);









		intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);









		intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);



















		/* always enable with pattern 1 (as per spec) */









		intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);








@@ -471,14 +467,14 @@ intel_dp_link_down(struct intel_encoder *encoder,







		intel_de_write(display, intel_dp->output_reg, intel_dp->DP);









		intel_de_posting_read(display, intel_dp->output_reg);



















		intel_wait_for_vblank_if_active(dev_priv, PIPE_A);









		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);









		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);









		intel_wait_for_vblank_if_active(display, PIPE_A);









		intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);









		intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);









	}



















	msleep(intel_dp->pps.panel_power_down_delay);



















	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))









	if (display->platform.valleyview || display->platform.cherryview)









		vlv_pps_port_disable(encoder, old_crtc_state);









}


















@@ -681,7 +677,6 @@ static void intel_enable_dp(struct intel_atomic_state *state,







			    const struct drm_connector_state *conn_state)









{









	struct intel_display *display = to_intel_display(state);









	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);









	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);









	u32 dp_reg = intel_de_read(display, intel_dp->output_reg);









	intel_wakeref_t wakeref;








@@ -690,7 +685,7 @@ static void intel_enable_dp(struct intel_atomic_state *state,







		return;



















	with_intel_pps_lock(intel_dp, wakeref) {









		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))









		if (display->platform.valleyview || display->platform.cherryview)









			vlv_pps_port_enable_unlocked(encoder, pipe_config);



















		intel_dp_enable_port(intel_dp, pipe_config);








@@ -700,13 +695,13 @@ static void intel_enable_dp(struct intel_atomic_state *state,







		intel_pps_vdd_off_unlocked(intel_dp, true);









	}



















	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {









	if (display->platform.valleyview || display->platform.cherryview) {









		unsigned int lane_mask = 0x0;



















		if (IS_CHERRYVIEW(dev_priv))









		if (display->platform.cherryview)









			lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);



















		vlv_wait_port_ready(display, dp_to_dig_port(intel_dp), lane_mask);









		vlv_wait_port_ready(encoder, lane_mask);









	}



















	intel_dp_set_power(intel_dp, DP_SET_POWER_D0);








@@ -1263,7 +1258,6 @@ static void intel_dp_encoder_destroy(struct drm_encoder *encoder)







static void intel_dp_encoder_reset(struct drm_encoder *encoder)









{









	struct intel_display *display = to_intel_display(encoder->dev);









	struct drm_i915_private *dev_priv = to_i915(encoder->dev);









	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));



















	intel_dp->DP = intel_de_read(display, intel_dp->output_reg);








@@ -1271,7 +1265,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)







	intel_dp->reset_link_params = true;









	intel_dp_invalidate_source_oui(intel_dp);



















	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))









	if (display->platform.valleyview || display->platform.cherryview)









		vlv_pps_pipe_reset(intel_dp);



















	intel_pps_encoder_reset(intel_dp);








@@ -1282,17 +1276,17 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = {







	.destroy = intel_dp_encoder_destroy,









};



















bool g4x_dp_init(struct drm_i915_private *dev_priv,









bool g4x_dp_init(struct intel_display *display,









		 i915_reg_t output_reg, enum port port)









{









	struct intel_display *display = &dev_priv->display;









	struct drm_i915_private *dev_priv = to_i915(display->drm);









	const struct intel_bios_encoder_data *devdata;









	struct intel_digital_port *dig_port;









	struct intel_encoder *intel_encoder;









	struct drm_encoder *encoder;









	struct intel_connector *intel_connector;



















	if (!assert_port_valid(dev_priv, port))









	if (!assert_port_valid(display, port))









		return false;



















	devdata = intel_bios_encoder_data_lookup(display, port);








@@ -1336,14 +1330,14 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,







	intel_encoder->suspend = intel_dp_encoder_suspend;









	intel_encoder->suspend_complete = g4x_dp_suspend_complete;









	intel_encoder->shutdown = intel_dp_encoder_shutdown;









	if (IS_CHERRYVIEW(dev_priv)) {









	if (display->platform.cherryview) {









		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;









		intel_encoder->pre_enable = chv_pre_enable_dp;









		intel_encoder->enable = vlv_enable_dp;









		intel_encoder->disable = vlv_disable_dp;









		intel_encoder->post_disable = chv_post_disable_dp;









		intel_encoder->post_pll_disable = chv_dp_post_pll_disable;









	} else if (IS_VALLEYVIEW(dev_priv)) {









	} else if (display->platform.valleyview) {









		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;









		intel_encoder->pre_enable = vlv_pre_enable_dp;









		intel_encoder->enable = vlv_enable_dp;








@@ -1358,24 +1352,24 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,







	intel_encoder->audio_enable = g4x_dp_audio_enable;









	intel_encoder->audio_disable = g4x_dp_audio_disable;



















	if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||









	if ((display->platform.ivybridge && port == PORT_A) ||









	    (HAS_PCH_CPT(dev_priv) && port != PORT_A))









		dig_port->dp.set_link_train = cpt_set_link_train;









	else









		dig_port->dp.set_link_train = g4x_set_link_train;



















	if (IS_CHERRYVIEW(dev_priv))









	if (display->platform.cherryview)









		intel_encoder->set_signal_levels = chv_set_signal_levels;









	else if (IS_VALLEYVIEW(dev_priv))









	else if (display->platform.valleyview)









		intel_encoder->set_signal_levels = vlv_set_signal_levels;









	else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)









	else if (display->platform.ivybridge && port == PORT_A)









		intel_encoder->set_signal_levels = ivb_cpu_edp_set_signal_levels;









	else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A)









	else if (display->platform.sandybridge && port == PORT_A)









		intel_encoder->set_signal_levels = snb_cpu_edp_set_signal_levels;









	else









		intel_encoder->set_signal_levels = g4x_set_signal_levels;



















	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||









	if (display->platform.valleyview || display->platform.cherryview ||









	    (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {









		dig_port->dp.preemph_max = intel_dp_preemph_max_3;









		dig_port->dp.voltage_max = intel_dp_voltage_max_3;








@@ -1388,8 +1382,8 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,







	dig_port->max_lanes = 4;



















	intel_encoder->type = INTEL_OUTPUT_DP;









	intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);









	if (IS_CHERRYVIEW(dev_priv)) {









	intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);









	if (display->platform.cherryview) {









		if (port == PORT_D)









			intel_encoder->pipe_mask = BIT(PIPE_C);









		else








@@ -1399,7 +1393,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,







	}









	intel_encoder->cloneable = 0;









	intel_encoder->port = port;









	intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);









	intel_encoder->hpd_pin = intel_hpd_pin_default(port);



















	dig_port->hpd_pulse = intel_dp_hpd_pulse;