Unverified Commit 1876c788 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'qcom-drivers-for-6.13-2' of... 

Merge tag 'qcom-drivers-for-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers

A few more Qualcomm driver updates for v6.13

Make the Adreno driver invoke the SMMU aperture setup firmware function,
which is required to allow the GPU to manage per-process page tables in
some firmware versions - as an example Rb3Gen2 has no GPU without this.

Add X1E Devkit to the list of devices that has functional EFI variable
access through the uefisecapp.

Flip the "manual slice configuration quirk" in the Qualcomm LLCC driver,
as this only applies to a single platform, and introduce support for
QCS8300, QCS615, SAR2130P, and SAR1130P.

Lastly, add IPQ5424 and IPQ5404 to the Qualcomm socinfo driver.

* tag 'qcom-drivers-for-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  soc: qcom: ice: Remove the device_link field in qcom_ice
  drm/msm/adreno: Setup SMMU aparture for per-process page table
  firmware: qcom: scm: Introduce CP_SMMU_APERTURE_ID
  soc: qcom: socinfo: add IPQ5424/IPQ5404 SoC ID
  dt-bindings: arm: qcom,ids: add SoC ID for IPQ5424/IPQ5404
  soc: qcom: llcc: Flip the manual slice configuration condition
  dt-bindings: firmware: qcom,scm: Document sm8750 SCM
  firmware: qcom: uefisecapp: Allow X1E Devkit devices
  soc: qcom: llcc: Add LLCC configuration for the QCS8300 platform
  dt-bindings: cache: qcom,llcc: Document the QCS8300 LLCC
  soc: qcom: llcc: Add configuration data for QCS615
  dt-bindings: cache: qcom,llcc: Document the QCS615 LLCC
  soc: qcom: llcc: add support for SAR2130P and SAR1130P
  soc: qcom: llcc: use deciman integers for bit shift values
  dt-bindings: cache: qcom,llcc: document SAR2130P and SAR1130P

Link: https://lore.kernel.org/r/20241113032425.356306-1-andersson@kernel.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents f335e015 54a8cd0f

Documentation/devicetree/bindings/cache/qcom,llcc.yaml

+32 −0
Original line number Diff line number Diff line
@@ -20,8 +20,12 @@ description: | 
properties:

  compatible:

    enum:

      - qcom,qcs615-llcc

      - qcom,qcs8300-llcc

      - qcom,qdu1000-llcc

      - qcom,sa8775p-llcc

      - qcom,sar1130p-llcc

      - qcom,sar2130p-llcc

      - qcom,sc7180-llcc

      - qcom,sc7280-llcc

      - qcom,sc8180x-llcc
@@ -67,6 +71,33 @@ allOf: 
        compatible:

          contains:

            enum:

              - qcom,sar1130p-llcc

              - qcom,sar2130p-llcc

    then:

      properties:

        reg:

          items:

            - description: LLCC0 base register region

            - description: LLCC1 base register region

            - description: LLCC broadcast OR register region

            - description: LLCC broadcast AND register region

            - description: LLCC scratchpad broadcast OR register region

            - description: LLCC scratchpad broadcast AND register region

        reg-names:

          items:

            - const: llcc0_base

            - const: llcc1_base

            - const: llcc_broadcast_base

            - const: llcc_broadcast_and_base

            - const: llcc_scratchpad_broadcast_base

            - const: llcc_scratchpad_broadcast_and_base



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,qcs615-llcc

              - qcom,sc7180-llcc

              - qcom,sm6350-llcc

    then:
@@ -165,6 +196,7 @@ allOf: 
        compatible:

          contains:

            enum:

              - qcom,qcs8300-llcc

              - qcom,sdm845-llcc

              - qcom,sm8150-llcc

              - qcom,sm8250-llcc

Documentation/devicetree/bindings/firmware/qcom,scm.yaml

+2 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ properties: 
          - qcom,scm-sm8450

          - qcom,scm-sm8550

          - qcom,scm-sm8650

          - qcom,scm-sm8750

          - qcom,scm-qcs404

          - qcom,scm-x1e80100

      - const: qcom,scm
@@ -198,6 +199,7 @@ allOf: 
                - qcom,scm-sm8450

                - qcom,scm-sm8550

                - qcom,scm-sm8650

                - qcom,scm-sm8750

    then:

      properties:

        interrupts: false

drivers/firmware/qcom/qcom_scm.c

+27 −0
Original line number Diff line number Diff line
@@ -903,6 +903,32 @@ int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) 
}

EXPORT_SYMBOL_GPL(qcom_scm_restore_sec_cfg);



#define QCOM_SCM_CP_APERTURE_CONTEXT_MASK	GENMASK(7, 0)



bool qcom_scm_set_gpu_smmu_aperture_is_available(void)

{

	return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP,

					    QCOM_SCM_MP_CP_SMMU_APERTURE_ID);

}

EXPORT_SYMBOL_GPL(qcom_scm_set_gpu_smmu_aperture_is_available);



int qcom_scm_set_gpu_smmu_aperture(unsigned int context_bank)

{

	struct qcom_scm_desc desc = {

		.svc = QCOM_SCM_SVC_MP,

		.cmd = QCOM_SCM_MP_CP_SMMU_APERTURE_ID,

		.arginfo = QCOM_SCM_ARGS(4),

		.args[0] = 0xffff0000 | FIELD_PREP(QCOM_SCM_CP_APERTURE_CONTEXT_MASK, context_bank),

		.args[1] = 0xffffffff,

		.args[2] = 0xffffffff,

		.args[3] = 0xffffffff,

		.owner = ARM_SMCCC_OWNER_SIP

	};



	return qcom_scm_call(__scm->dev, &desc, NULL);

}

EXPORT_SYMBOL_GPL(qcom_scm_set_gpu_smmu_aperture);



int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)

{

	struct qcom_scm_desc desc = {
@@ -1740,6 +1766,7 @@ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = { 
	{ .compatible = "microsoft,romulus13", },

	{ .compatible = "microsoft,romulus15", },

	{ .compatible = "qcom,sc8180x-primus" },

	{ .compatible = "qcom,x1e001de-devkit" },

	{ .compatible = "qcom,x1e80100-crd" },

	{ .compatible = "qcom,x1e80100-qcp" },

	{ }

drivers/firmware/qcom/qcom_scm.h

+1 −0
Original line number Diff line number Diff line
@@ -116,6 +116,7 @@ struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void); 
#define QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE	0x05

#define QCOM_SCM_MP_VIDEO_VAR			0x08

#define QCOM_SCM_MP_ASSIGN			0x16

#define QCOM_SCM_MP_CP_SMMU_APERTURE_ID		0x1b

#define QCOM_SCM_MP_SHM_BRIDGE_ENABLE		0x1c

#define QCOM_SCM_MP_SHM_BRIDGE_DELETE		0x1d

#define QCOM_SCM_MP_SHM_BRIDGE_CREATE		0x1e

drivers/gpu/drm/msm/adreno/adreno_gpu.c

+11 −0
Original line number Diff line number Diff line
@@ -572,8 +572,19 @@ struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, 


int adreno_hw_init(struct msm_gpu *gpu)

{

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);

	int ret;



	VERB("%s", gpu->name);



	if (adreno_gpu->info->family >= ADRENO_6XX_GEN1 &&

	    qcom_scm_set_gpu_smmu_aperture_is_available()) {

		/* We currently always use context bank 0, so hard code this */

		ret = qcom_scm_set_gpu_smmu_aperture(0);

		if (ret)

			DRM_DEV_ERROR(gpu->dev->dev, "unable to set SMMU aperture: %d\n", ret);

	}



	for (int i = 0; i < gpu->nr_rings; i++) {

		struct msm_ringbuffer *ring = gpu->rb[i];