Commit 188db3d7 authored by Akhil P Oommen's avatar Akhil P Oommen Committed by Rob Clark
Browse files

drm/msm/a6xx: Rebase GMU register offsets 



GMU registers are always at a fixed offset from the GPU base address,
a consistency maintained at least within a given architecture generation.
In A8x family, the base address of the GMU has changed, but the offsets
of the gmu registers remain largely the same. To enable reuse of the gmu
code for A8x chipsets, update the gmu register offsets to be relative
to the GPU's base address instead of GMU's.

Signed-off-by: default avatarAkhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689010/


Message-ID: <20251118-kaana-gpu-support-v4-10-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
parent 1ef05ef9

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

+57 −43
Original line number Diff line number Diff line
@@ -610,22 +610,19 @@ static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) 
	writel(value, ptr + (offset << 2));

}



static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,

		const char *name);



static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)

{

	struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);

	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

	struct platform_device *pdev = to_platform_device(gmu->dev);

	void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");

	void __iomem *pdcptr = devm_platform_ioremap_resource_byname(pdev, "gmu_pdc");

	u32 seqmem0_drv0_reg = REG_A6XX_RSCC_SEQ_MEM_0_DRV0;

	void __iomem *seqptr = NULL;

	uint32_t pdc_address_offset;

	bool pdc_in_aop = false;



	if (IS_ERR(pdcptr))

		goto err;

		return;



	if (adreno_is_a650_family(adreno_gpu) ||

	    adreno_is_a7xx(adreno_gpu))
@@ -638,9 +635,9 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) 
		pdc_address_offset = 0x30080;



	if (!pdc_in_aop) {

		seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");

		seqptr = devm_platform_ioremap_resource_byname(pdev, "gmu_pdc_seq");

		if (IS_ERR(seqptr))

			goto err;

			return;

	}



	/* Disable SDE clock gating */
@@ -730,12 +727,6 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) 


	/* ensure no writes happen before the uCode is fully written */

	wmb();



err:

	if (!IS_ERR_OR_NULL(pdcptr))

		iounmap(pdcptr);

	if (!IS_ERR_OR_NULL(seqptr))

		iounmap(seqptr);

}



/*
@@ -1821,27 +1812,6 @@ static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) 
	return 0;

}



static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,

		const char *name)

{

	void __iomem *ret;

	struct resource *res = platform_get_resource_byname(pdev,

			IORESOURCE_MEM, name);



	if (!res) {

		DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);

		return ERR_PTR(-EINVAL);

	}



	ret = ioremap(res->start, resource_size(res));

	if (!ret) {

		DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);

		return ERR_PTR(-EINVAL);

	}



	return ret;

}



static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,

		const char *name, irq_handler_t handler)

{
@@ -1892,7 +1862,6 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) 
{

	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

	struct platform_device *pdev = to_platform_device(gmu->dev);



	mutex_lock(&gmu->lock);

	if (!gmu->initialized) {
@@ -1921,8 +1890,6 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) 
		qmp_put(gmu->qmp);



	iounmap(gmu->mmio);

	if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))

		iounmap(gmu->rscc);

	gmu->mmio = NULL;

	gmu->rscc = NULL;
@@ -1949,10 +1916,38 @@ static int cxpd_notifier_cb(struct notifier_block *nb, 
	return 0;

}



static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,

		const char *name, resource_size_t *start)

{

	void __iomem *ret;

	struct resource *res = platform_get_resource_byname(pdev,

			IORESOURCE_MEM, name);



	if (!res) {

		DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);

		return ERR_PTR(-EINVAL);

	}



	ret = ioremap(res->start, resource_size(res));

	if (!ret) {

		DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);

		return ERR_PTR(-EINVAL);

	}



	if (start)

		*start = res->start;



	return ret;

}



int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)

{

	struct platform_device *pdev = of_find_device_by_node(node);

	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

	struct msm_gpu *gpu = &adreno_gpu->base;

	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

	resource_size_t start;

	struct resource *res;

	int ret;



	if (!pdev)
@@ -1977,12 +1972,21 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 
	gmu->nr_clocks = ret;



	/* Map the GMU registers */

	gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");

	gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu", &start);

	if (IS_ERR(gmu->mmio)) {

		ret = PTR_ERR(gmu->mmio);

		goto err_mmio;

	}



	res = platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM, "kgsl_3d0_reg_memory");

	if (!res) {

		ret = -EINVAL;

		goto err_mmio;

	}



	/* Identify gmu base offset from gpu base address */

	gmu->mmio_offset = (u32)(start - res->start);



	gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx");

	if (IS_ERR(gmu->cxpd)) {

		ret = PTR_ERR(gmu->cxpd);
@@ -2024,10 +2028,13 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 


int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)

{

	struct platform_device *pdev = of_find_device_by_node(node);

	struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;

	struct msm_gpu *gpu = &adreno_gpu->base;

	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

	struct platform_device *pdev = of_find_device_by_node(node);

	struct device_link *link;

	resource_size_t start;

	struct resource *res;

	int ret;



	if (!pdev)
@@ -2122,15 +2129,24 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 
		goto err_memory;



	/* Map the GMU registers */

	gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");

	gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu", &start);

	if (IS_ERR(gmu->mmio)) {

		ret = PTR_ERR(gmu->mmio);

		goto err_memory;

	}



	res = platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM, "kgsl_3d0_reg_memory");

	if (!res) {

		ret = -EINVAL;

		goto err_mmio;

	}



	/* Identify gmu base offset from gpu base address */

	gmu->mmio_offset = (u32)(start - res->start);



	if (adreno_is_a650_family(adreno_gpu) ||

	    adreno_is_a7xx(adreno_gpu)) {

		gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");

		gmu->rscc = devm_platform_ioremap_resource_byname(pdev, "rscc");

		if (IS_ERR(gmu->rscc)) {

			ret = -ENODEV;

			goto err_mmio;
@@ -2208,8 +2224,6 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 


err_mmio:

	iounmap(gmu->mmio);

	if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))

		iounmap(gmu->rscc);

	free_irq(gmu->gmu_irq, gmu);

	free_irq(gmu->hfi_irq, gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.h

+12 −8
Original line number Diff line number Diff line
@@ -68,6 +68,7 @@ struct a6xx_gmu { 
	struct drm_gpuvm *vm;



	void __iomem *mmio;

	u32 mmio_offset;

	void __iomem *rscc;



	int hfi_irq;
@@ -130,20 +131,23 @@ struct a6xx_gmu { 
	unsigned long status;

};



#define GMU_BYTE_OFFSET(gmu, offset) (((offset) << 2) - (gmu)->mmio_offset)



static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)

{

	return readl(gmu->mmio + (offset << 2));

	/* The 'offset' is based on GPU's start address. Adjust it */

	return readl(gmu->mmio + GMU_BYTE_OFFSET(gmu, offset));

}



static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)

{

	writel(value, gmu->mmio + (offset << 2));

	writel(value, gmu->mmio + GMU_BYTE_OFFSET(gmu, offset));

}



static inline void

gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size)

{

	memcpy_toio(gmu->mmio + (offset << 2), data, size);

	memcpy_toio(gmu->mmio + GMU_BYTE_OFFSET(gmu, offset), data, size);

	wmb();

}
@@ -160,17 +164,17 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi) 
{

	u64 val;



	val = (u64) readl(gmu->mmio + (lo << 2));

	val |= ((u64) readl(gmu->mmio + (hi << 2)) << 32);

	val = gmu_read(gmu, lo);

	val |= ((u64) gmu_read(gmu, hi) << 32);



	return val;

}



#define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \

	readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \

		interval, timeout)

	readl_poll_timeout((gmu)->mmio + (GMU_BYTE_OFFSET(gmu, addr)), val, \

		cond, interval, timeout)

#define gmu_poll_timeout_atomic(gmu, addr, val, cond, interval, timeout) \

	readl_poll_timeout_atomic((gmu)->mmio + ((addr) << 2), val, cond, \

	readl_poll_timeout_atomic((gmu)->mmio + (GMU_BYTE_OFFSET(gmu, addr)), val, cond, \

		interval, timeout)



static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h

+28 −28
Original line number Diff line number Diff line
@@ -343,48 +343,48 @@ static const struct a6xx_registers a6xx_gbif_reglist = 


static const u32 a6xx_gmu_gx_registers[] = {

	/* GMU GX */

	0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b,

	0x001e, 0x001e, 0x0020, 0x0023, 0x0026, 0x0026, 0x0028, 0x002b,

	0x002e, 0x002e, 0x0030, 0x0033, 0x0036, 0x0036, 0x0038, 0x003b,

	0x003e, 0x003e, 0x0040, 0x0043, 0x0046, 0x0046, 0x0080, 0x0084,

	0x0100, 0x012b, 0x0140, 0x0140,

	0x1a800, 0x1a800, 0x1a810, 0x1a813, 0x1a816, 0x1a816, 0x1a818, 0x1a81b,

	0x1a81e, 0x1a81e, 0x1a820, 0x1a823, 0x1a826, 0x1a826, 0x1a828, 0x1a82b,

	0x1a82e, 0x1a82e, 0x1a830, 0x1a833, 0x1a836, 0x1a836, 0x1a838, 0x1a83b,

	0x1a83e, 0x1a83e, 0x1a840, 0x1a843, 0x1a846, 0x1a846, 0x1a880, 0x1a884,

	0x1a900, 0x1a92b, 0x1a940, 0x1a940,

};



static const u32 a6xx_gmu_cx_registers[] = {

	/* GMU CX */

	0x4c00, 0x4c07, 0x4c10, 0x4c12, 0x4d00, 0x4d00, 0x4d07, 0x4d0a,

	0x5000, 0x5004, 0x5007, 0x5008, 0x500b, 0x500c, 0x500f, 0x501c,

	0x5024, 0x502a, 0x502d, 0x5030, 0x5040, 0x5053, 0x5087, 0x5089,

	0x50a0, 0x50a2, 0x50a4, 0x50af, 0x50c0, 0x50c3, 0x50d0, 0x50d0,

	0x50e4, 0x50e4, 0x50e8, 0x50ec, 0x5100, 0x5103, 0x5140, 0x5140,

	0x5142, 0x5144, 0x514c, 0x514d, 0x514f, 0x5151, 0x5154, 0x5154,

	0x5157, 0x5158, 0x515d, 0x515d, 0x5162, 0x5162, 0x5164, 0x5165,

	0x5180, 0x5186, 0x5190, 0x519e, 0x51c0, 0x51c0, 0x51c5, 0x51cc,

	0x51e0, 0x51e2, 0x51f0, 0x51f0, 0x5200, 0x5201,

	0x1f400, 0x1f407, 0x1f410, 0x1f412, 0x1f500, 0x1f500, 0x1f507, 0x1f50a,

	0x1f800, 0x1f804, 0x1f807, 0x1f808, 0x1f80b, 0x1f80c, 0x1f80f, 0x1f81c,

	0x1f824, 0x1f82a, 0x1f82d, 0x1f830, 0x1f840, 0x1f853, 0x1f887, 0x1f889,

	0x1f8a0, 0x1f8a2, 0x1f8a4, 0x1f8af, 0x1f8c0, 0x1f8c3, 0x1f8d0, 0x1f8d0,

	0x1f8e4, 0x1f8e4, 0x1f8e8, 0x1f8ec, 0x1f900, 0x1f903, 0x1f940, 0x1f940,

	0x1f942, 0x1f944, 0x1f94c, 0x1f94d, 0x1f94f, 0x1f951, 0x1f954, 0x1f954,

	0x1f957, 0x1f958, 0x1f95d, 0x1f95d, 0x1f962, 0x1f962, 0x1f964, 0x1f965,

	0x1f980, 0x1f986, 0x1f990, 0x1f99e, 0x1f9c0, 0x1f9c0, 0x1f9c5, 0x1f9cc,

	0x1f9e0, 0x1f9e2, 0x1f9f0, 0x1f9f0, 0x1fa00, 0x1fa01,

	/* GMU AO */

	0x9300, 0x9316, 0x9400, 0x9400,

	0x23b00, 0x23b16, 0x23c00, 0x23c00,

};



static const u32 a6xx_gmu_gpucc_registers[] = {

	/* GPU CC */

	0x9800, 0x9812, 0x9840, 0x9852, 0x9c00, 0x9c04, 0x9c07, 0x9c0b,

	0x9c15, 0x9c1c, 0x9c1e, 0x9c2d, 0x9c3c, 0x9c3d, 0x9c3f, 0x9c40,

	0x9c42, 0x9c49, 0x9c58, 0x9c5a, 0x9d40, 0x9d5e, 0xa000, 0xa002,

	0xa400, 0xa402, 0xac00, 0xac02, 0xb000, 0xb002, 0xb400, 0xb402,

	0xb800, 0xb802,

	0x24000, 0x24012, 0x24040, 0x24052, 0x24400, 0x24404, 0x24407, 0x2440b,

	0x24415, 0x2441c, 0x2441e, 0x2442d, 0x2443c, 0x2443d, 0x2443f, 0x24440,

	0x24442, 0x24449, 0x24458, 0x2445a, 0x24540, 0x2455e, 0x24800, 0x24802,

	0x24c00, 0x24c02, 0x25400, 0x25402, 0x25800, 0x25802, 0x25c00, 0x25c02,

	0x26000, 0x26002,

	/* GPU CC ACD */

	0xbc00, 0xbc16, 0xbc20, 0xbc27,

	0x26400, 0x26416, 0x26420, 0x26427,

};



static const u32 a621_gmu_gpucc_registers[] = {

	/* GPU CC */

	0x9800, 0x980e, 0x9c00, 0x9c0e, 0xb000, 0xb004, 0xb400, 0xb404,

	0xb800, 0xb804, 0xbc00, 0xbc05, 0xbc14, 0xbc1d, 0xbc2a, 0xbc30,

	0xbc32, 0xbc32, 0xbc41, 0xbc55, 0xbc66, 0xbc68, 0xbc78, 0xbc7a,

	0xbc89, 0xbc8a, 0xbc9c, 0xbc9e, 0xbca0, 0xbca3, 0xbcb3, 0xbcb5,

	0xbcc5, 0xbcc7, 0xbcd6, 0xbcd8, 0xbce8, 0xbce9, 0xbcf9, 0xbcfc,

	0xbd0b, 0xbd0c, 0xbd1c, 0xbd1e, 0xbd40, 0xbd70, 0xbe00, 0xbe16,

	0xbe20, 0xbe2d,

	0x24000, 0x2400e, 0x24400, 0x2440e, 0x25800, 0x25804, 0x25c00, 0x25c04,

	0x26000, 0x26004, 0x26400, 0x26405, 0x26414, 0x2641d, 0x2642a, 0x26430,

	0x26432, 0x26432, 0x26441, 0x26455, 0x26466, 0x26468, 0x26478, 0x2647a,

	0x26489, 0x2648a, 0x2649c, 0x2649e, 0x264a0, 0x264a3, 0x264b3, 0x264b5,

	0x264c5, 0x264c7, 0x264d6, 0x264d8, 0x264e8, 0x264e9, 0x264f9, 0x264fc,

	0x2650b, 0x2650c, 0x2651c, 0x2651e, 0x26540, 0x26570, 0x26600, 0x26616,

	0x26620, 0x2662d,

};



static const u32 a6xx_gmu_cx_rscc_registers[] = {

drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml

+124 −124

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