Unverified Commit 18efe86b authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "RISC-V: Detect and report speed of unaligned vector accesses" 

Charlie Jenkins <charlie@rivosinc.com> says:

Adds support for detecting and reporting the speed of unaligned vector
accesses on RISC-V CPUs. Adds vec_misaligned_speed key to the hwprobe
adds Zicclsm to cpufeature and fixes the check for scalar unaligned
emulated all CPUs. The vec_misaligned_speed key keeps the same format
as the scalar unaligned access speed key.

This set does not emulate unaligned vector accesses on CPUs that do not
support them. Only reports if userspace can run them and speed of
unaligned vector accesses if supported.

* b4-shazam-merge:
  RISC-V: hwprobe: Document unaligned vector perf key
  RISC-V: Report vector unaligned access speed hwprobe
  RISC-V: Detect unaligned vector accesses supported
  RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED
  RISC-V: Scalar unaligned access emulated on hotplug CPUs
  RISC-V: Check scalar unaligned access on all CPUs

Link: https://lore.kernel.org/r/20241017-jesse_unaligned_vector-v10-0-5b33500160f8@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents 77270206 40e09ebd

Documentation/arch/riscv/hwprobe.rst

+16 −0
Original line number Diff line number Diff line
@@ -274,3 +274,19 @@ The following keys are defined: 
  represent the highest userspace virtual address usable.



* :c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time CSR`.



* :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`: An enum value describing the

     performance of misaligned vector accesses on the selected set of processors.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of misaligned

    vector accesses is unknown.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW`: 32-bit misaligned accesses using vector

    registers are slower than the equivalent quantity of byte accesses via vector registers.

    Misaligned accesses may be supported directly in hardware, or trapped and emulated by software.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_FAST`: 32-bit misaligned accesses using vector

    registers are faster than the equivalent quantity of byte accesses via vector registers.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are

    not supported at all and will generate a misaligned address fault.

arch/riscv/Kconfig

+56 −2
Original line number Diff line number Diff line
@@ -786,10 +786,24 @@ config THREAD_SIZE_ORDER 


config RISCV_MISALIGNED

	bool

	help

	  Embed support for detecting and emulating misaligned

	  scalar or vector loads and stores.



config RISCV_SCALAR_MISALIGNED

	bool

	select RISCV_MISALIGNED

	select SYSCTL_ARCH_UNALIGN_ALLOW

	help

	  Embed support for emulating misaligned loads and stores.



config RISCV_VECTOR_MISALIGNED

	bool

	select RISCV_MISALIGNED

	depends on RISCV_ISA_V

	help

	  Enable detecting support for vector misaligned loads and stores.



choice

	prompt "Unaligned Accesses Support"

	default RISCV_PROBE_UNALIGNED_ACCESS
@@ -801,7 +815,7 @@ choice 


config RISCV_PROBE_UNALIGNED_ACCESS

	bool "Probe for hardware unaligned access support"

	select RISCV_MISALIGNED

	select RISCV_SCALAR_MISALIGNED

	help

	  During boot, the kernel will run a series of tests to determine the

	  speed of unaligned accesses. This probing will dynamically determine
@@ -812,7 +826,7 @@ config RISCV_PROBE_UNALIGNED_ACCESS 


config RISCV_EMULATED_UNALIGNED_ACCESS

	bool "Emulate unaligned access where system support is missing"

	select RISCV_MISALIGNED

	select RISCV_SCALAR_MISALIGNED

	help

	  If unaligned memory accesses trap into the kernel as they are not

	  supported by the system, the kernel will emulate the unaligned
@@ -841,6 +855,46 @@ config RISCV_EFFICIENT_UNALIGNED_ACCESS 


endchoice



choice

	prompt "Vector unaligned Accesses Support"

	depends on RISCV_ISA_V

	default RISCV_PROBE_VECTOR_UNALIGNED_ACCESS

	help

	  This determines the level of support for vector unaligned accesses. This

	  information is used by the kernel to perform optimizations. It is also

	  exposed to user space via the hwprobe syscall. The hardware will be

	  probed at boot by default.



config RISCV_PROBE_VECTOR_UNALIGNED_ACCESS

	bool "Probe speed of vector unaligned accesses"

	select RISCV_VECTOR_MISALIGNED

	depends on RISCV_ISA_V

	help

	  During boot, the kernel will run a series of tests to determine the

	  speed of vector unaligned accesses if they are supported. This probing

	  will dynamically determine the speed of vector unaligned accesses on

	  the underlying system if they are supported.



config RISCV_SLOW_VECTOR_UNALIGNED_ACCESS

	bool "Assume the system supports slow vector unaligned memory accesses"

	depends on NONPORTABLE

	help

	  Assume that the system supports slow vector unaligned memory accesses. The

	  kernel and userspace programs may not be able to run at all on systems

	  that do not support unaligned memory accesses.



config RISCV_EFFICIENT_VECTOR_UNALIGNED_ACCESS

	bool "Assume the system supports fast vector unaligned memory accesses"

	depends on NONPORTABLE

	help

	  Assume that the system supports fast vector unaligned memory accesses. When

	  enabled, this option improves the performance of the kernel on such

	  systems. However, the kernel and userspace programs will run much more

	  slowly, or will not be able to run at all, on systems that do not

	  support efficient unaligned memory accesses.



endchoice



source "arch/riscv/Kconfig.vendor"



endmenu # "Platform type"

arch/riscv/include/asm/cpufeature.h

+9 −1
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 


#include <linux/bitmap.h>

#include <linux/jump_label.h>

#include <linux/workqueue.h>

#include <asm/hwcap.h>

#include <asm/alternative-macros.h>

#include <asm/errno.h>
@@ -58,8 +59,9 @@ void __init riscv_user_isa_enable(void); 
#define __RISCV_ISA_EXT_SUPERSET_VALIDATE(_name, _id, _sub_exts, _validate) \

	_RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), _validate)



#if defined(CONFIG_RISCV_MISALIGNED)

bool check_unaligned_access_emulated_all_cpus(void);

#if defined(CONFIG_RISCV_SCALAR_MISALIGNED)

void check_unaligned_access_emulated(struct work_struct *work __always_unused);

void unaligned_emulation_finish(void);

bool unaligned_ctl_available(void);

DECLARE_PER_CPU(long, misaligned_access_speed);
@@ -70,6 +72,12 @@ static inline bool unaligned_ctl_available(void) 
}

#endif



bool check_vector_unaligned_access_emulated_all_cpus(void);

#if defined(CONFIG_RISCV_VECTOR_MISALIGNED)

void check_vector_unaligned_access_emulated(struct work_struct *work __always_unused);

DECLARE_PER_CPU(long, vector_misaligned_access);

#endif



#if defined(CONFIG_RISCV_PROBE_UNALIGNED_ACCESS)

DECLARE_STATIC_KEY_FALSE(fast_unaligned_access_speed_key);

arch/riscv/include/asm/entry-common.h

+0 −11
Original line number Diff line number Diff line
@@ -25,18 +25,7 @@ static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs, 
void handle_page_fault(struct pt_regs *regs);

void handle_break(struct pt_regs *regs);



#ifdef CONFIG_RISCV_MISALIGNED

int handle_misaligned_load(struct pt_regs *regs);

int handle_misaligned_store(struct pt_regs *regs);

#else

static inline int handle_misaligned_load(struct pt_regs *regs)

{

	return -1;

}

static inline int handle_misaligned_store(struct pt_regs *regs)

{

	return -1;

}

#endif



#endif /* _ASM_RISCV_ENTRY_COMMON_H */

arch/riscv/include/asm/hwprobe.h

+1 −1
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ 


#include <uapi/asm/hwprobe.h>



#define RISCV_HWPROBE_MAX_KEY 9

#define RISCV_HWPROBE_MAX_KEY 10



static inline bool riscv_hwprobe_key_is_valid(__s64 key)

{