Unverified Commit 1a974547 authored by Yoshihiro Shimoda's avatar Yoshihiro Shimoda Committed by Krzysztof Wilczyński
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PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting 

dw_pcie_setup() is already setting PCI_EXP_LNKCAP_MLW to pcie->num_lanes
in the PCI_EXP_LNKCAP register for programming maximum link width.

Hence, remove the redundant setting here.

Link: https://lore.kernel.org/linux-pci/20231018085631.1121289-5-yoshihiro.shimoda.uh@renesas.com


Signed-off-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarSerge Semin <fancer.lancer@gmail.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
parent 89db0793

drivers/pci/controller/dwc/pcie-tegra194.c

+0 −6
Original line number Diff line number Diff line
@@ -917,12 +917,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp) 
		AMBA_ERROR_RESPONSE_CRS_SHIFT);

	dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val);



	/* Configure Max lane width from DT */

	val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);

	val &= ~PCI_EXP_LNKCAP_MLW;

	val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT);

	dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);



	/* Clear Slot Clock Configuration bit if SRNS configuration */

	if (pcie->enable_srns) {

		val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +