Commit 1b324635 authored by Austin Zheng's avatar Austin Zheng Committed by Alex Deucher
Browse files

drm/amd/display: Refactor VActive implementation 



[Why & How]
Refactors VActive accounting in PMO, and breaks down fill time
requirement by P-State type as it can result in drasitcally different
bandwidth requirements depending on the blackout length.

Reviewed-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarAustin Zheng <Austin.Zheng@amd.com>
Signed-off-by: default avatarRay Wu <ray.wu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e44ee152

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h

+10 −2
Original line number Diff line number Diff line
@@ -87,6 +87,15 @@ enum dml2_output_link_dp_rate { 
	dml2_dp_rate_uhbr20 = 6

};



enum dml2_pstate_type {

	dml2_pstate_type_uclk = 0,

	dml2_pstate_type_fclk = 1,

	dml2_pstate_type_ppt = 2,

	dml2_pstate_type_temp_read = 3,

	dml2_pstate_type_dummy_pstate = 4,

	dml2_pstate_type_count = 5

};



enum dml2_uclk_pstate_change_strategy {

	dml2_uclk_pstate_change_strategy_auto = 0,

	dml2_uclk_pstate_change_strategy_force_vactive = 1,
@@ -393,8 +402,7 @@ struct dml2_plane_parameters { 
		// reserved_vblank_time_ns is the minimum time to reserve in vblank for Twait

		// The actual reserved vblank time used for the corresponding stream in mode_programming would be at least as much as this per-plane override.

		long reserved_vblank_time_ns;

		unsigned int max_vactive_det_fill_delay_us; // 0 = no reserved time, +ve = explicit max delay

		unsigned int vactive_latency_to_hide_for_pstate_admissibility_us;

		unsigned int max_vactive_det_fill_delay_us[dml2_pstate_type_count]; // 0 = no reserved time, +ve = explicit max delay

		unsigned int gpuvm_min_page_size_kbytes;

		unsigned int hostvm_min_page_size_kbytes;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h

+1 −1
Original line number Diff line number Diff line
@@ -191,7 +191,7 @@ struct dml2_ip_capabilities { 
	unsigned int subvp_prefetch_end_to_mall_start_us;

	unsigned int subvp_fw_processing_delay;

	unsigned int max_vactive_det_fill_delay_us;

	unsigned int ppt_max_allow_delay_ns;

	unsigned int ppt_max_allow_delay_us;

	unsigned int temp_read_max_allow_delay_us;

	unsigned int dummy_pstate_max_allow_delay_us;

	/* FAMS2 delays */

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h

+0 −8
Original line number Diff line number Diff line
@@ -195,14 +195,6 @@ struct dml2_mcache_surface_allocation { 
	} informative;

};



enum dml2_pstate_type {

	dml2_pstate_type_uclk,

	dml2_pstate_type_ppt,

	dml2_pstate_type_temp_read,

	dml2_pstate_type_dummy_pstate,

	dml2_pstate_type_count

};



enum dml2_pstate_method {

	dml2_pstate_method_na = 0,

	/* hw exclusive modes */

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

+19 −18
Original line number Diff line number Diff line
@@ -6972,7 +6972,7 @@ static void calculate_bytes_to_fetch_required_to_hide_latency( 








		stream_index = p->display_cfg->plane_descriptors[plane_index].stream_index;

















		dst_lines_to_hide = (unsigned int)math_ceil(p->latency_to_hide_us /









		dst_lines_to_hide = (unsigned int)math_ceil(p->latency_to_hide_us[0] /









			((double)p->display_cfg->stream_descriptors[stream_index].timing.h_total /









				(double)p->display_cfg->stream_descriptors[stream_index].timing.pixel_clock_khz * 1000.0));
















@@ -7069,9 +7069,9 @@ static void calculate_excess_vactive_bandwidth_required(







		excess_vactive_fill_bw_l[plane_index] = 0.0;









		excess_vactive_fill_bw_c[plane_index] = 0.0;

















		if (display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us > 0) {









			excess_vactive_fill_bw_l[plane_index] = (double)bytes_required_l[plane_index] / (double)display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us;









			excess_vactive_fill_bw_c[plane_index] = (double)bytes_required_c[plane_index] / (double)display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us;









		if (display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk] > 0) {









			excess_vactive_fill_bw_l[plane_index] = (double)bytes_required_l[plane_index] / (double)display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk];









			excess_vactive_fill_bw_c[plane_index] = (double)bytes_required_c[plane_index] / (double)display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk];









		}









	}









}








@@ -9051,11 +9051,11 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out







	calculate_bytes_to_fetch_required_to_hide_latency_params->swath_width_c = mode_lib->ms.SwathWidthC;









	calculate_bytes_to_fetch_required_to_hide_latency_params->swath_height_l = mode_lib->ms.SwathHeightY;









	calculate_bytes_to_fetch_required_to_hide_latency_params->swath_height_c = mode_lib->ms.SwathHeightC;









	calculate_bytes_to_fetch_required_to_hide_latency_params->latency_to_hide_us = mode_lib->soc.power_management_parameters.dram_clk_change_blackout_us;









	calculate_bytes_to_fetch_required_to_hide_latency_params->latency_to_hide_us[0] = mode_lib->soc.power_management_parameters.dram_clk_change_blackout_us;

















	/* outputs */









	calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_l = s->pstate_bytes_required_l;









	calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_c = s->pstate_bytes_required_c;









	calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_l = s->pstate_bytes_required_l[dml2_pstate_type_uclk];









	calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_c = s->pstate_bytes_required_c[dml2_pstate_type_uclk];

















	calculate_bytes_to_fetch_required_to_hide_latency(calculate_bytes_to_fetch_required_to_hide_latency_params);
















@@ -9063,8 +9063,8 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out







	calculate_excess_vactive_bandwidth_required(









			display_cfg,









			mode_lib->ms.num_active_planes,









			s->pstate_bytes_required_l,









			s->pstate_bytes_required_c,









			s->pstate_bytes_required_l[dml2_pstate_type_uclk],









			s->pstate_bytes_required_c[dml2_pstate_type_uclk],









			/* outputs */









			mode_lib->ms.excess_vactive_fill_bw_l,









			mode_lib->ms.excess_vactive_fill_bw_c);








@@ -9506,8 +9506,8 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out







	calculate_vactive_det_fill_latency(









			display_cfg,









			mode_lib->ms.num_active_planes,









			s->pstate_bytes_required_l,









			s->pstate_bytes_required_c,









			s->pstate_bytes_required_l[dml2_pstate_type_uclk],









			s->pstate_bytes_required_c[dml2_pstate_type_uclk],









			mode_lib->ms.dcc_dram_bw_nom_overhead_factor_p0,









			mode_lib->ms.dcc_dram_bw_nom_overhead_factor_p1,









			mode_lib->ms.vactive_sw_bw_l,








@@ -9515,7 +9515,7 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out







			mode_lib->ms.surface_avg_vactive_required_bw,









			mode_lib->ms.surface_peak_required_bw,









			/* outputs */









			mode_lib->ms.dram_change_vactive_det_fill_delay_us);









			mode_lib->ms.pstate_vactive_det_fill_delay_us[dml2_pstate_type_uclk]);

















#ifdef __DML_VBA_DEBUG__









	DML_LOG_VERBOSE("DML::%s: max_urgent_latency_us = %f\n", __func__, s->mSOCParameters.max_urgent_latency_us);








@@ -11009,11 +11009,11 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex







	calculate_bytes_to_fetch_required_to_hide_latency_params->swath_width_c = mode_lib->mp.SwathWidthC;









	calculate_bytes_to_fetch_required_to_hide_latency_params->swath_height_l = mode_lib->mp.SwathHeightY;









	calculate_bytes_to_fetch_required_to_hide_latency_params->swath_height_c = mode_lib->mp.SwathHeightC;









	calculate_bytes_to_fetch_required_to_hide_latency_params->latency_to_hide_us = mode_lib->soc.power_management_parameters.dram_clk_change_blackout_us;









	calculate_bytes_to_fetch_required_to_hide_latency_params->latency_to_hide_us[0] = mode_lib->soc.power_management_parameters.dram_clk_change_blackout_us;

















	/* outputs */









	calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_l = s->pstate_bytes_required_l;









	calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_c = s->pstate_bytes_required_c;









	calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_l = s->pstate_bytes_required_l[dml2_pstate_type_uclk];









	calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_c = s->pstate_bytes_required_c[dml2_pstate_type_uclk];

















	calculate_bytes_to_fetch_required_to_hide_latency(calculate_bytes_to_fetch_required_to_hide_latency_params);
















@@ -11021,8 +11021,8 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex







	calculate_excess_vactive_bandwidth_required(









			display_cfg,









			s->num_active_planes,









			s->pstate_bytes_required_l,









			s->pstate_bytes_required_c,









			s->pstate_bytes_required_l[dml2_pstate_type_uclk],









			s->pstate_bytes_required_c[dml2_pstate_type_uclk],









			/* outputs */









			mode_lib->mp.excess_vactive_fill_bw_l,









			mode_lib->mp.excess_vactive_fill_bw_c);








@@ -12943,7 +12943,8 @@ void dml2_core_calcs_get_plane_support_info(const struct dml2_display_cfg *displ















	out->active_latency_hiding_us = (int)mode_lib->ms.VActiveLatencyHidingUs[plane_idx];

















	out->dram_change_vactive_det_fill_delay_us = (unsigned int)math_ceil(mode_lib->ms.dram_change_vactive_det_fill_delay_us[plane_idx]);









	out->vactive_det_fill_delay_us[dml2_pstate_type_uclk] =









			(unsigned int)math_ceil(mode_lib->ms.pstate_vactive_det_fill_delay_us[plane_idx][dml2_pstate_type_uclk]);









}

















void dml2_core_calcs_get_stream_support_info(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct core_stream_support_info *out, int plane_index)

























drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h



+8
−8






























Original line number
Diff line number
Diff line







@@ -593,7 +593,7 @@ struct dml2_core_internal_mode_support {







	double VActiveLatencyHidingMargin[DML2_MAX_PLANES];









	double VActiveLatencyHidingUs[DML2_MAX_PLANES];









	unsigned int MaxVStartupLines[DML2_MAX_PLANES];









	double dram_change_vactive_det_fill_delay_us[DML2_MAX_PLANES];









	double pstate_vactive_det_fill_delay_us[dml2_pstate_type_count][DML2_MAX_PLANES];



















	unsigned int num_mcaches_l[DML2_MAX_PLANES];









	unsigned int mcache_row_bytes_l[DML2_MAX_PLANES];








@@ -623,8 +623,8 @@ struct dml2_core_internal_mode_support {







	unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES];









	unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES];



















	unsigned int pstate_bytes_required_l[DML2_MAX_PLANES];









	unsigned int pstate_bytes_required_c[DML2_MAX_PLANES];









	unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES];









	unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES];









	unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES];









	unsigned int cursor_bytes_per_line[DML2_MAX_PLANES];


















@@ -1138,8 +1138,8 @@ struct dml2_core_calcs_mode_support_locals {







	unsigned int cursor_bytes[DML2_MAX_PLANES];









	bool stream_visited[DML2_MAX_PLANES];



















	unsigned int pstate_bytes_required_l[DML2_MAX_PLANES];









	unsigned int pstate_bytes_required_c[DML2_MAX_PLANES];









	unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES];









	unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES];



















	double prefetch_sw_bytes[DML2_MAX_PLANES];









	double Tpre_rounded[DML2_MAX_PLANES];








@@ -1230,8 +1230,8 @@ struct dml2_core_calcs_mode_programming_locals {







	double Tr0_trips_flip_rounded[DML2_MAX_PLANES];









	unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES];



















	unsigned int pstate_bytes_required_l[DML2_MAX_PLANES];









	unsigned int pstate_bytes_required_c[DML2_MAX_PLANES];









	unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES];









	unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES];



















	double prefetch_sw_bytes[DML2_MAX_PLANES];









	double Tpre_rounded[DML2_MAX_PLANES];








@@ -2253,7 +2253,7 @@ struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params







	unsigned int *swath_width_c;









	unsigned int *swath_height_l;









	unsigned int *swath_height_c;









	double latency_to_hide_us;









	double latency_to_hide_us[DML2_MAX_PLANES];



















	/* outputs */









	unsigned int *bytes_required_l;