Commit 1c63df24 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pci-v7.0-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci 

Pull pci fixes from Bjorn Helgaas:

 - Update MAINTAINERS email address (Shawn Guo)

 - Refresh cached Endpoint driver MSI Message Address to fix a v7.0
   regression when kernel changes the address after firmware has
   configured it (Niklas Cassel)

 - Flush Endpoint MSI-X writes so they complete before the outbound ATU
   entry is unmapped (Niklas Cassel)

 - Correct the PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value, which broke VMM use
   of PCI capabilities (Bjorn Helgaas)

* tag 'pci-v7.0-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci:
  PCI: Correct PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value
  PCI: dwc: ep: Flush MSI-X write before unmapping its ATU entry
  PCI: dwc: ep: Refresh MSI Message Address cache on change
  MAINTAINERS: Update Shawn Guo's address for HiSilicon PCIe controller driver
parents aed968f8 39195990

MAINTAINERS

+1 −1
Original line number Diff line number Diff line
@@ -20507,7 +20507,7 @@ F: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml 
F:	drivers/pci/controller/dwc/pcie-kirin.c









PCIE DRIVER FOR HISILICON STB









M:	Shawn Guo <shawn.guo@linaro.org>









M:	Shawn Guo <shawnguo@kernel.org>









L:	linux-pci@vger.kernel.org









S:	Maintained









F:	Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt

























drivers/pci/controller/dwc/pcie-designware-ep.c



+16
−9






























Original line number
Diff line number
Diff line







@@ -905,6 +905,19 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,







	 * supported, so we avoid reprogramming the region on every MSI,









	 * specifically unmapping immediately after writel().









	 */









	if (ep->msi_iatu_mapped && (ep->msi_msg_addr != msg_addr ||









				    ep->msi_map_size != map_size)) {









		/*









		 * The host changed the MSI target address or the required









		 * mapping size changed. Reprogramming the iATU when there are









		 * operations in flight is unsafe on this controller. However,









		 * there is no unified way to check if we have operations in









		 * flight, thus we don't know if we should WARN() or not.









		 */









		dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys);









		ep->msi_iatu_mapped = false;









	}



















	if (!ep->msi_iatu_mapped) {









		ret = dw_pcie_ep_map_addr(epc, func_no, 0,









					  ep->msi_mem_phys, msg_addr,








@@ -915,15 +928,6 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,







		ep->msi_iatu_mapped = true;









		ep->msi_msg_addr = msg_addr;









		ep->msi_map_size = map_size;









	} else if (WARN_ON_ONCE(ep->msi_msg_addr != msg_addr ||









				ep->msi_map_size != map_size)) {









		/*









		 * The host changed the MSI target address or the required









		 * mapping size changed. Reprogramming the iATU at runtime is









		 * unsafe on this controller, so bail out instead of trying to









		 * update the existing region.









		 */









		return -EINVAL;









	}



















	writel(msg_data | (interrupt_num - 1), ep->msi_mem + offset);








@@ -1010,6 +1014,9 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,

















	writel(msg_data, ep->msi_mem + offset);



















	/* flush posted write before unmap */









	readl(ep->msi_mem + offset);



















	dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys);



















	return 0;
































include/uapi/linux/pci_regs.h



+1
−1






























Original line number
Diff line number
Diff line







@@ -712,7 +712,7 @@







#define  PCI_EXP_LNKCTL2_HASD		0x0020 /* HW Autonomous Speed Disable */









#define PCI_EXP_LNKSTA2		0x32	/* Link Status 2 */









#define  PCI_EXP_LNKSTA2_FLIT		0x0400 /* Flit Mode Status */









#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2	0x32	/* end of v2 EPs w/ link */









#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2	0x34	/* end of v2 EPs w/ link */









#define PCI_EXP_SLTCAP2		0x34	/* Slot Capabilities 2 */









#define  PCI_EXP_SLTCAP2_IBPD	0x00000001 /* In-band PD Disable Supported */









#define PCI_EXP_SLTCTL2		0x38	/* Slot Control 2 */