Commit 1ccbf135 authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/psr: Enable ALPM on source side for eDP Panel replay 



Enable ALPM AUX-Less on source side for Panel Replay eDP. Also write all
calculated AUX-Less configuration values accordingly. Enabling it on sink
side is in upcoming patch.

Bspec: 71477

v5:
  - mention enable is only on source side in commit message
v4:
  - add comment explaining why AUX less is enabled on eDP panel replay
    without any extra checks
v3:
  - do not use alpm_ctl as uninitialized variable
v2:
  - do not set AUX-Wake related bits for AUX-Less case
  - drop switch to active latency
  - add SLEEP_HOLD_TIME_50_SYMBOLS
  - add PORT_ALPM_CTL_MAX_PHY_SWING_HOLD

Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarAnimesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240328141928.1311284-5-jouni.hogander@intel.com
parent 0dd21f83

drivers/gpu/drm/i915/display/intel_psr.c

+43 −4
Original line number Diff line number Diff line
@@ -1721,14 +1721,43 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp) 
	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

	struct intel_psr *psr = &intel_dp->psr;

	u32 alpm_ctl;



	if (DISPLAY_VER(dev_priv) < 20)

		return;



	intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder),

		       ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |

		       ALPM_CTL_ALPM_ENTRY_CHECK(psr->alpm_parameters.check_entry_lines) |

		       ALPM_CTL_EXTENDED_FAST_WAKE_TIME(psr->alpm_parameters.fast_wake_lines));

	/*

	 * Panel Replay on eDP is always using ALPM aux less. I.e. no need to

	 * check panel support at this point.

	 */

	if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) {

		alpm_ctl = ALPM_CTL_ALPM_ENABLE |

			ALPM_CTL_ALPM_AUX_LESS_ENABLE |

			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS;



		intel_de_write(dev_priv, PORT_ALPM_CTL(cpu_transcoder),

			       PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |

			       PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |

			       PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |

			       PORT_ALPM_CTL_SILENCE_PERIOD(

				       psr->alpm_parameters.silence_period_sym_clocks));



		intel_de_write(dev_priv, PORT_ALPM_LFPS_CTL(cpu_transcoder),

			       PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |

			       PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(

				       psr->alpm_parameters.lfps_half_cycle_num_of_syms) |

			       PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(

				       psr->alpm_parameters.lfps_half_cycle_num_of_syms) |

			       PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(

				       psr->alpm_parameters.lfps_half_cycle_num_of_syms));

	} else {

		alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |

			ALPM_CTL_EXTENDED_FAST_WAKE_TIME(psr->alpm_parameters.fast_wake_lines);

	}



	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(psr->alpm_parameters.check_entry_lines);



	intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder), alpm_ctl);

}



static void intel_psr_enable_source(struct intel_dp *intel_dp,
@@ -1996,6 +2025,16 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) 


	intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false);



	/* Panel Replay on eDP is always using ALPM aux less. */

	if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) {

		intel_de_rmw(dev_priv, ALPM_CTL(cpu_transcoder),

			     ALPM_CTL_ALPM_ENABLE |

			     ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0);



		intel_de_rmw(dev_priv, PORT_ALPM_CTL(cpu_transcoder),

			     PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0);

	}



	/* Disable PSR on Sink */

	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);