Unverified Commit 1cdfe53d authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'at91-soc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/arm 

Microchip arm-soc updates for v6.18

This update includes:
- low priority fixes to the PM code, in relation to recent addition of
  sam9x75 or sama7d65 SoCs
- removal of the 2.5V regulator for low power modes since this is
  no longer supported

* tag 'at91-soc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  ARM: at91: pm: Remove 2.5V regulator
  ARM: at91: pm: save and restore ACR during PLL disable/enable
  ARM: at91: pm: fix MCKx restore routine
  ARM: at91: pm: fix .uhp_udp_mask specification for current SoCs

Link: https://lore.kernel.org/r/20250916150328.27015-1-nicolas.ferre@microchip.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 9685b297 74743675

arch/arm/mach-at91/pm.c

+1 −1
Original line number Diff line number Diff line
@@ -1364,7 +1364,7 @@ static const struct pmc_info pmc_infos[] __initconst = { 
		.version = AT91_PMC_V1,

	},

	{

		.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,

		.uhp_udp_mask = AT91SAM926x_PMC_UHP,

		.mckr = 0x28,

		.version = AT91_PMC_V2,

	},

arch/arm/mach-at91/pm_suspend.S

+9 −32
Original line number Diff line number Diff line
@@ -87,29 +87,6 @@ tmp3 .req r6 


	.endm



/**

 * Set state for 2.5V low power regulator

 * @ena: 0 - disable regulator

 *	 1 - enable regulator

 *

 * Side effects: overwrites r7, r8, r9, r10

 */

	.macro at91_2_5V_reg_set_low_power ena

#ifdef CONFIG_SOC_SAMA7

	ldr	r7, .sfrbu

	mov	r8, #\ena

	ldr	r9, [r7, #AT91_SFRBU_25LDOCR]

	orr	r9, r9, #AT91_SFRBU_25LDOCR_LP

	cmp	r8, #1

	beq	lp_done_\ena

	bic	r9, r9, #AT91_SFRBU_25LDOCR_LP

lp_done_\ena:

	ldr	r10, =AT91_SFRBU_25LDOCR_LDOANAKEY

	orr	r9, r9, r10

	str	r9, [r7, #AT91_SFRBU_25LDOCR]

#endif

	.endm



	.macro at91_backup_set_lpm reg

#ifdef CONFIG_SOC_SAMA7

	orr	\reg, \reg, #0x200000
@@ -689,6 +666,10 @@ sr_dis_exit: 
	bic	tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID

	str	tmp2, [pmc, #AT91_PMC_PLL_UPDT]



	/* save acr */

	ldr	tmp2, [pmc, #AT91_PMC_PLL_ACR]

	str	tmp2, .saved_acr



	/* save div. */

	mov	tmp1, #0

	ldr	tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
@@ -758,7 +739,7 @@ sr_dis_exit: 
	str	tmp1, [pmc, #AT91_PMC_PLL_UPDT]



	/* step 2. */

	ldr	tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA

	ldr	tmp1, .saved_acr

	str	tmp1, [pmc, #AT91_PMC_PLL_ACR]



	/* step 3. */
@@ -904,7 +885,7 @@ e_done: 
/**

 * at91_mckx_ps_restore: restore MCKx settings

 *

 * Side effects: overwrites tmp1, tmp2

 * Side effects: overwrites tmp1, tmp2 and tmp3

 */

.macro at91_mckx_ps_restore

#ifdef CONFIG_SOC_SAMA7
@@ -980,7 +961,7 @@ r_ps: 
	bic	tmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK

	orr	tmp3, tmp3, tmp1

	orr	tmp3, tmp3, #AT91_PMC_MCR_V2_CMD

	str	tmp2, [pmc, #AT91_PMC_MCR_V2]

	str	tmp3, [pmc, #AT91_PMC_MCR_V2]



	wait_mckrdy tmp1
@@ -1019,9 +1000,6 @@ save_mck: 


	at91_plla_disable



	/* Enable low power mode for 2.5V regulator. */

	at91_2_5V_reg_set_low_power 1



	ldr	tmp3, .pm_mode

	cmp	tmp3, #AT91_PM_ULP1

	beq	ulp1_mode
@@ -1034,9 +1012,6 @@ ulp1_mode: 
	b	ulp_exit



ulp_exit:

	/* Disable low power mode for 2.5V regulator. */

	at91_2_5V_reg_set_low_power 0



	ldr	pmc, .pmc_base



	at91_plla_enable
@@ -1207,6 +1182,8 @@ ENDPROC(at91_pm_suspend_in_sram) 
#endif

.saved_mckr:

	.word 0

.saved_acr:

	.word 0

.saved_pllar:

	.word 0

.saved_sam9_lpr:

include/soc/at91/sama7-sfrbu.h

+0 −7
Original line number Diff line number Diff line
@@ -18,13 +18,6 @@ 
#define		AT91_SFRBU_PSWBU_SOFTSWITCH	(1 << 1)	/* Power switch BU source selection */

#define		AT91_SFRBU_PSWBU_CTRL		(1 << 0)	/* Power switch BU control */



#define AT91_SFRBU_25LDOCR			(0x0C)		/* SFRBU 2.5V LDO Control Register */

#define		AT91_SFRBU_25LDOCR_LDOANAKEY	(0x3B6E18 << 8)	/* Specific value mandatory to allow writing of other register bits. */

#define		AT91_SFRBU_25LDOCR_STATE	(1 << 3)	/* LDOANA Switch On/Off Control */

#define		AT91_SFRBU_25LDOCR_LP		(1 << 2)	/* LDOANA Low-Power Mode Control */

#define		AT91_SFRBU_PD_VALUE_MSK		(0x3)

#define		AT91_SFRBU_25LDOCR_PD_VALUE(v)	((v) & AT91_SFRBU_PD_VALUE_MSK)	/* LDOANA Pull-down value */



#define AT91_FRBU_DDRPWR			(0x10)		/* SFRBU DDR Power Control Register */

#define		AT91_FRBU_DDRPWR_STATE		(1 << 0)	/* DDR Power Mode State */