Commit 1d4ce63e authored by Aleksa Paunovic's avatar Aleksa Paunovic Committed by Paul Walmsley
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riscv: Add xmipsexectl instructions 



Add xmipsexectl instruction opcodes. This includes the MIPS.PAUSE,
MIPS.EHB, and MIPS.IHB instructions.

Signed-off-by: default avatarAleksa Paunovic <aleksa.paunovic@htecgroup.com>
Reviewed-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20250724-p8700-pause-v5-3-a6cbbe1c3412@htecgroup.com


Signed-off-by: default avatarPaul Walmsley <pjw@kernel.org>
parent a8fed1bc

arch/riscv/include/asm/vendor_extensions/mips.h

+19 −0
Original line number Diff line number Diff line
@@ -15,4 +15,23 @@ struct riscv_isa_vendor_ext_data_list; 
extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips;

#endif



/* Extension specific instructions */



/*

 * All of the xmipsexectl extension instructions are

 * ‘hint’ encodings of the SLLI instruction,

 * with rd = 0, rs1 = 0 and imm = 1 for IHB, imm = 3 for EHB,

 * and imm = 5 for PAUSE.

 * MIPS.PAUSE is an alternative opcode which is implemented to have the

 * same behavior as PAUSE on some MIPS RISCV cores.

 * MIPS.EHB clears all execution hazards before allowing

 * any subsequent instructions to execute.

 * MIPS.IHB clears all instruction hazards before

 * allowing any subsequent instructions to fetch.

 */



#define MIPS_PAUSE	".4byte 0x00501013\n\t"

#define MIPS_EHB	".4byte 0x00301013\n\t"

#define MIPS_IHB	".4byte 0x00101013\n\t"



#endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H