Commit 1dbd59f3 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: Add psp v13_0_14 ip block 



Add psp v13_0_14 ip block support.

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarLe Ma <le.ma@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3d1bb1a2

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+1 −0
Original line number Diff line number Diff line
@@ -1851,6 +1851,7 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(13, 0, 8):

	case IP_VERSION(13, 0, 10):

	case IP_VERSION(13, 0, 11):

	case IP_VERSION(13, 0, 14):

	case IP_VERSION(14, 0, 0):

	case IP_VERSION(14, 0, 1):

		amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+10 −3
Original line number Diff line number Diff line
@@ -145,6 +145,7 @@ static int psp_init_sriov_microcode(struct psp_context *psp) 
		adev->virt.autoload_ucode_id = 0;

		break;

	case IP_VERSION(13, 0, 6):

	case IP_VERSION(13, 0, 14):

		ret = psp_init_cap_microcode(psp, ucode_prefix);

		ret &= psp_init_ta_microcode(psp, ucode_prefix);

		break;
@@ -207,6 +208,7 @@ static int psp_early_init(void *handle) 
		psp->boot_time_tmr = false;

		fallthrough;

	case IP_VERSION(13, 0, 6):

	case IP_VERSION(13, 0, 14):

		psp_v13_0_set_psp_funcs(psp);

		psp->autoload_supported = false;

		break;
@@ -355,7 +357,8 @@ static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 
	bool ret = false;

	int i;



	if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6))

	if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||

	    amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))

		return false;



	db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
@@ -847,6 +850,7 @@ static bool psp_skip_tmr(struct psp_context *psp) 
	case IP_VERSION(13, 0, 2):

	case IP_VERSION(13, 0, 6):

	case IP_VERSION(13, 0, 10):

	case IP_VERSION(13, 0, 14):

		return true;

	default:

		return false;
@@ -1450,7 +1454,9 @@ int psp_xgmi_get_topology_info(struct psp_context *psp, 
			(psp->xgmi_context.supports_extended_data &&

			 get_extended_data) ||

			amdgpu_ip_version(psp->adev, MP0_HWIP, 0) ==

				IP_VERSION(13, 0, 6);

				IP_VERSION(13, 0, 6) ||

			amdgpu_ip_version(psp->adev, MP0_HWIP, 0) ==

				IP_VERSION(13, 0, 14);

		bool ta_port_num_support = amdgpu_sriov_vf(psp->adev) ? 0 :

				psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG;
@@ -2636,7 +2642,8 @@ static int psp_load_p2s_table(struct psp_context *psp) 
				(adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)))

		return 0;



	if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) {

	if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||

	    amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) {

		uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D :

								0x0036003C;

		if (psp->sos.fw_version < supp_vers)

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+2 −0
Original line number Diff line number Diff line
@@ -3053,6 +3053,7 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) 
		switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {

		case IP_VERSION(13, 0, 2):

		case IP_VERSION(13, 0, 6):

		case IP_VERSION(13, 0, 14):

			return true;

		default:

			return false;
@@ -3064,6 +3065,7 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) 
		case IP_VERSION(13, 0, 0):

		case IP_VERSION(13, 0, 6):

		case IP_VERSION(13, 0, 10):

		case IP_VERSION(13, 0, 14):

			return true;

		default:

			return false;

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

+9 −3
Original line number Diff line number Diff line
@@ -51,6 +51,8 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); 
MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");

MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin");

MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin");

MODULE_FIRMWARE("amdgpu/psp_13_0_14_sos.bin");

MODULE_FIRMWARE("amdgpu/psp_13_0_14_ta.bin");

MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");

MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");

MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin");
@@ -115,6 +117,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp) 
	case IP_VERSION(13, 0, 6):

	case IP_VERSION(13, 0, 7):

	case IP_VERSION(13, 0, 10):

	case IP_VERSION(13, 0, 14):

		err = psp_init_sos_microcode(psp, ucode_prefix);

		if (err)

			return err;
@@ -168,7 +171,8 @@ static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 
	int retry_loop, retry_cnt, ret;



	retry_cnt =

		(amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) ?

		((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||

		  amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))) ?

			PSP_VMBX_POLLING_LIMIT :

			10;

	/* Wait for bootloader to signify that it is ready having bit 31 of
@@ -193,7 +197,8 @@ static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp) 
	struct amdgpu_device *adev = psp->adev;

	int ret;



	if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) {

	if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||

	    amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) {

		ret = psp_v13_0_wait_for_vmbx_ready(psp);

		if (ret)

			amdgpu_ras_query_boot_status(adev, 4);
@@ -787,7 +792,8 @@ static bool psp_v13_0_get_ras_capability(struct psp_context *psp) 
	if (!con)

		return false;



	if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) &&

	if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||

	     amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) &&

	    (!(adev->flags & AMD_IS_APU))) {

		reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127);

		adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0));

drivers/gpu/drm/amd/amdgpu/soc15.c

+2 −1
Original line number Diff line number Diff line
@@ -1458,7 +1458,8 @@ static void soc15_common_get_clockgating_state(void *handle, u64 *flags) 
		adev->hdp.funcs->get_clock_gating_state(adev, flags);



	if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) &&

	    (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))) {

	    (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) &&

	    (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14))) {

		/* AMD_CG_SUPPORT_DRM_MGCG */

		data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));

		if (!(data & 0x01000000))