Commit 1e9124df authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-fixes-2022-06-20' of https://gitlab.freedesktop.org/drm/msm into drm-fixes 



Fixes for v5.19-rc4

- Workaround for parade DSI bridge power sequencing
- Fix for multi-planar YUV format offsets
- Limiting WB modes to max sspp linewidth
- Fixing the supported rotations to add 180 back for IGT
- Fix to handle pm_runtime_get_sync() errors to avoid unclocked access
  in the bind() path for dpu driver
- Fix the irq_free() without request issue which was a being hit frequently
  in CI.
- Fix to add minimum ICC vote in the msm_mdss pm_resume path to address
  bootup splats
- Fix to avoid dereferencing without checking in WB encoder
- Fix to avoid crash during suspend in DP driver by ensuring interrupt
  mask bits are updated
- Remove unused code from dpu_encoder_virt_atomic_check()
- Fix to remove redundant init of dsc variable
- Fix to ensure mmap offset is initialized to avoid memory corruption
  from unpin/evict
- Fix double runpm disable in probe-defer path
- VMA fenced-unpin fixes
- Fix for WB max-width
- Fix for rare dp resolution change issue

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvdsOF1-+WfTWyEyu33XPcvxOCU00G-dz7EF2J+fdyUHg@mail.gmail.com
parents 08d27daa a6e2af64

drivers/gpu/drm/msm/adreno/adreno_gpu.c

+10 −4
Original line number Diff line number Diff line
@@ -498,10 +498,15 @@ int adreno_hw_init(struct msm_gpu *gpu) 


		ring->cur = ring->start;

		ring->next = ring->start;



		/* reset completed fence seqno: */

		ring->memptrs->fence = ring->fctx->completed_fence;

		ring->memptrs->rptr = 0;



		/* Detect and clean up an impossible fence, ie. if GPU managed

		 * to scribble something invalid, we don't want that to confuse

		 * us into mistakingly believing that submits have completed.

		 */

		if (fence_before(ring->fctx->last_fence, ring->memptrs->fence)) {

			ring->memptrs->fence = ring->fctx->last_fence;

		}

	}



	return 0;
@@ -1057,6 +1062,7 @@ void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) 
	for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)

		release_firmware(adreno_gpu->fw[i]);



	if (pm_runtime_enabled(&priv->gpu_pdev->dev))

		pm_runtime_disable(&priv->gpu_pdev->dev);



	msm_gpu_cleanup(&adreno_gpu->base);

drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c

+8 −1
Original line number Diff line number Diff line
@@ -11,7 +11,14 @@ static int dpu_wb_conn_get_modes(struct drm_connector *connector) 
	struct msm_drm_private *priv = dev->dev_private;

	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);



	return drm_add_modes_noedid(connector, dpu_kms->catalog->caps->max_linewidth,

	/*

	 * We should ideally be limiting the modes only to the maxlinewidth but

	 * on some chipsets this will allow even 4k modes to be added which will

	 * fail the per SSPP bandwidth checks. So, till we have dual-SSPP support

	 * and source split support added lets limit the modes based on max_mixer_width

	 * as 4K modes can then be supported.

	 */

	return drm_add_modes_noedid(connector, dpu_kms->catalog->caps->max_mixer_width,

			dev->mode_config.max_height);

}

drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

+2 −0
Original line number Diff line number Diff line
@@ -216,6 +216,7 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms, 
		encoder = mdp4_lcdc_encoder_init(dev, panel_node);

		if (IS_ERR(encoder)) {

			DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n");

			of_node_put(panel_node);

			return PTR_ERR(encoder);

		}
@@ -225,6 +226,7 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms, 
		connector = mdp4_lvds_connector_init(dev, panel_node, encoder);

		if (IS_ERR(connector)) {

			DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n");

			of_node_put(panel_node);

			return PTR_ERR(connector);

		}

drivers/gpu/drm/msm/dp/dp_ctrl.c

+25 −8
Original line number Diff line number Diff line
@@ -1534,6 +1534,8 @@ static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl) 
	return ret;

}



static int dp_ctrl_on_stream_phy_test_report(struct dp_ctrl *dp_ctrl);



static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl)

{

	int ret = 0;
@@ -1557,7 +1559,7 @@ static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) 


	ret = dp_ctrl_on_link(&ctrl->dp_ctrl);

	if (!ret)

		ret = dp_ctrl_on_stream(&ctrl->dp_ctrl);

		ret = dp_ctrl_on_stream_phy_test_report(&ctrl->dp_ctrl);

	else

		DRM_ERROR("failed to enable DP link controller\n");
@@ -1813,7 +1815,27 @@ static int dp_ctrl_link_retrain(struct dp_ctrl_private *ctrl) 
	return dp_ctrl_setup_main_link(ctrl, &training_step);

}



int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl)

static int dp_ctrl_on_stream_phy_test_report(struct dp_ctrl *dp_ctrl)

{

	int ret;

	struct dp_ctrl_private *ctrl;



	ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);



	ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;



	ret = dp_ctrl_enable_stream_clocks(ctrl);

	if (ret) {

		DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);

		return ret;

	}



	dp_ctrl_send_phy_test_pattern(ctrl);



	return 0;

}



int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train)

{

	int ret = 0;

	bool mainlink_ready = false;
@@ -1849,12 +1871,7 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl) 
		goto end;

	}



	if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {

		dp_ctrl_send_phy_test_pattern(ctrl);

		return 0;

	}



	if (!dp_ctrl_channel_eq_ok(ctrl))

	if (force_link_train || !dp_ctrl_channel_eq_ok(ctrl))

		dp_ctrl_link_retrain(ctrl);



	/* stop txing train pattern to end link training */

drivers/gpu/drm/msm/dp/dp_ctrl.h

+1 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ struct dp_ctrl { 
};



int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl);

int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl);

int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train);

int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl);

int dp_ctrl_off_link(struct dp_ctrl *dp_ctrl);

int dp_ctrl_off(struct dp_ctrl *dp_ctrl);