Commit 1f82e8e1 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'x86/msr' into x86/core, to resolve conflicts 



 Conflicts:
	arch/x86/boot/startup/sme.c
	arch/x86/coco/sev/core.c
	arch/x86/kernel/fpu/core.c
	arch/x86/kernel/fpu/xstate.c

 Semantic conflict:
	arch/x86/include/asm/sev-internal.h

Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents 34be7519 9cf78722

arch/x86/boot/startup/sme.c

+2 −2
Original line number Diff line number Diff line
@@ -523,7 +523,7 @@ void __head sme_enable(struct boot_params *bp) 
	me_mask = 1UL << (ebx & 0x3f);



	/* Check the SEV MSR whether SEV or SME is enabled */

	sev_status = msr = __rdmsr(MSR_AMD64_SEV);

	sev_status = msr = native_rdmsrq(MSR_AMD64_SEV);

	feature_mask = (msr & MSR_AMD64_SEV_ENABLED) ? AMD_SEV_BIT : AMD_SME_BIT;



	/*
@@ -554,7 +554,7 @@ void __head sme_enable(struct boot_params *bp) 
			return;



		/* For SME, check the SYSCFG MSR */

		msr = __rdmsr(MSR_AMD64_SYSCFG);

		msr = native_rdmsrq(MSR_AMD64_SYSCFG);

		if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))

			return;

	}

arch/x86/coco/sev/core.c

+2 −1
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ 
#include <asm/apic.h>

#include <asm/cpuid.h>

#include <asm/cmdline.h>

#include <asm/msr.h>



/* AP INIT values as documented in the APM2  section "Processor Initialization State" */

#define AP_INIT_CS_LIMIT		0xffff
@@ -2039,7 +2040,7 @@ void __init snp_secure_tsc_init(void) 
		return;



	setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);

	rdmsrl(MSR_AMD64_GUEST_TSC_FREQ, tsc_freq_mhz);

	rdmsrq(MSR_AMD64_GUEST_TSC_FREQ, tsc_freq_mhz);

	snp_tsc_freq_khz = (unsigned long)(tsc_freq_mhz * 1000);



	x86_platform.calibrate_cpu = securetsc_get_tsc_khz;

arch/x86/events/amd/brs.c

+6 −6
Original line number Diff line number Diff line
@@ -44,12 +44,12 @@ static inline unsigned int brs_to(int idx) 
static __always_inline void set_debug_extn_cfg(u64 val)

{

	/* bits[4:3] must always be set to 11b */

	__wrmsr(MSR_AMD_DBG_EXTN_CFG, val | 3ULL << 3, val >> 32);

	native_wrmsrq(MSR_AMD_DBG_EXTN_CFG, val | 3ULL << 3);

}



static __always_inline u64 get_debug_extn_cfg(void)

{

	return __rdmsr(MSR_AMD_DBG_EXTN_CFG);

	return native_rdmsrq(MSR_AMD_DBG_EXTN_CFG);

}



static bool __init amd_brs_detect(void)
@@ -187,7 +187,7 @@ void amd_brs_reset(void) 
	/*

	 * Mark first entry as poisoned

	 */

	wrmsrl(brs_to(0), BRS_POISON);

	wrmsrq(brs_to(0), BRS_POISON);

}



int __init amd_brs_init(void)
@@ -325,7 +325,7 @@ void amd_brs_drain(void) 
		u32 brs_idx = tos - i;

		u64 from, to;



		rdmsrl(brs_to(brs_idx), to);

		rdmsrq(brs_to(brs_idx), to);



		/* Entry does not belong to us (as marked by kernel) */

		if (to == BRS_POISON)
@@ -341,7 +341,7 @@ void amd_brs_drain(void) 
		if (!amd_brs_match_plm(event, to))

			continue;



		rdmsrl(brs_from(brs_idx), from);

		rdmsrq(brs_from(brs_idx), from);



		perf_clear_branch_entry_bitfields(br+nr);
@@ -371,7 +371,7 @@ static void amd_brs_poison_buffer(void) 
	idx = amd_brs_get_tos(&cfg);



	/* Poison target of entry */

	wrmsrl(brs_to(idx), BRS_POISON);

	wrmsrq(brs_to(idx), BRS_POISON);

}



/*

arch/x86/events/amd/core.c

+7 −6
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/jiffies.h>

#include <asm/apicdef.h>

#include <asm/apic.h>

#include <asm/msr.h>

#include <asm/nmi.h>



#include "../perf_event.h"
@@ -563,13 +564,13 @@ static void amd_pmu_cpu_reset(int cpu) 
		return;



	/* Clear enable bits i.e. PerfCntrGlobalCtl.PerfCntrEn */

	wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0);

	wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0);



	/*

	 * Clear freeze and overflow bits i.e. PerfCntrGLobalStatus.LbrFreeze

	 * and PerfCntrGLobalStatus.PerfCntrOvfl

	 */

	wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR,

	wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR,

	       GLOBAL_STATUS_LBRS_FROZEN | amd_pmu_global_cntr_mask);

}
@@ -651,7 +652,7 @@ static void amd_pmu_cpu_dead(int cpu) 


static __always_inline void amd_pmu_set_global_ctl(u64 ctl)

{

	wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, ctl);

	wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, ctl);

}



static inline u64 amd_pmu_get_global_status(void)
@@ -659,7 +660,7 @@ static inline u64 amd_pmu_get_global_status(void) 
	u64 status;



	/* PerfCntrGlobalStatus is read-only */

	rdmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, status);

	rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, status);



	return status;

}
@@ -672,14 +673,14 @@ static inline void amd_pmu_ack_global_status(u64 status) 
	 * clears the same bit in PerfCntrGlobalStatus

	 */



	wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, status);

	wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, status);

}



static bool amd_pmu_test_overflow_topbit(int idx)

{

	u64 counter;



	rdmsrl(x86_pmu_event_addr(idx), counter);

	rdmsrq(x86_pmu_event_addr(idx), counter);



	return !(counter & BIT_ULL(x86_pmu.cntval_bits - 1));

}

arch/x86/events/amd/ibs.c

+14 −13
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <linux/sched/clock.h>



#include <asm/apic.h>

#include <asm/msr.h>



#include "../perf_event.h"
@@ -424,7 +425,7 @@ perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event, 
	 * prev count manually on overflow.

	 */

	while (!perf_event_try_update(event, count, 64)) {

		rdmsrl(event->hw.config_base, *config);

		rdmsrq(event->hw.config_base, *config);

		count = perf_ibs->get_count(*config);

	}

}
@@ -435,9 +436,9 @@ static inline void perf_ibs_enable_event(struct perf_ibs *perf_ibs, 
	u64 tmp = hwc->config | config;



	if (perf_ibs->fetch_count_reset_broken)

		wrmsrl(hwc->config_base, tmp & ~perf_ibs->enable_mask);

		wrmsrq(hwc->config_base, tmp & ~perf_ibs->enable_mask);



	wrmsrl(hwc->config_base, tmp | perf_ibs->enable_mask);

	wrmsrq(hwc->config_base, tmp | perf_ibs->enable_mask);

}



/*
@@ -452,9 +453,9 @@ static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs, 
{

	config &= ~perf_ibs->cnt_mask;

	if (boot_cpu_data.x86 == 0x10)

		wrmsrl(hwc->config_base, config);

		wrmsrq(hwc->config_base, config);

	config &= ~perf_ibs->enable_mask;

	wrmsrl(hwc->config_base, config);

	wrmsrq(hwc->config_base, config);

}



/*
@@ -513,7 +514,7 @@ static void perf_ibs_stop(struct perf_event *event, int flags) 
	if (!stopping && (hwc->state & PERF_HES_UPTODATE))

		return;



	rdmsrl(hwc->config_base, config);

	rdmsrq(hwc->config_base, config);



	if (stopping) {

		/*
@@ -1256,7 +1257,7 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs) 
	hwc = &event->hw;

	msr = hwc->config_base;

	buf = ibs_data.regs;

	rdmsrl(msr, *buf);

	rdmsrq(msr, *buf);

	if (!(*buf++ & perf_ibs->valid_mask))

		goto fail;
@@ -1274,7 +1275,7 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs) 
	offset_max = perf_ibs_get_offset_max(perf_ibs, event, check_rip);



	do {

		rdmsrl(msr + offset, *buf++);

		rdmsrq(msr + offset, *buf++);

		size++;

		offset = find_next_bit(perf_ibs->offset_mask,

				       perf_ibs->offset_max,
@@ -1304,17 +1305,17 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs) 
	if (event->attr.sample_type & PERF_SAMPLE_RAW) {

		if (perf_ibs == &perf_ibs_op) {

			if (ibs_caps & IBS_CAPS_BRNTRGT) {

				rdmsrl(MSR_AMD64_IBSBRTARGET, *buf++);

				rdmsrq(MSR_AMD64_IBSBRTARGET, *buf++);

				br_target_idx = size;

				size++;

			}

			if (ibs_caps & IBS_CAPS_OPDATA4) {

				rdmsrl(MSR_AMD64_IBSOPDATA4, *buf++);

				rdmsrq(MSR_AMD64_IBSOPDATA4, *buf++);

				size++;

			}

		}

		if (perf_ibs == &perf_ibs_fetch && (ibs_caps & IBS_CAPS_FETCHCTLEXTD)) {

			rdmsrl(MSR_AMD64_ICIBSEXTDCTL, *buf++);

			rdmsrq(MSR_AMD64_ICIBSEXTDCTL, *buf++);

			size++;

		}

	}
@@ -1565,7 +1566,7 @@ static inline int ibs_eilvt_valid(void) 


	preempt_disable();



	rdmsrl(MSR_AMD64_IBSCTL, val);

	rdmsrq(MSR_AMD64_IBSCTL, val);

	offset = val & IBSCTL_LVT_OFFSET_MASK;



	if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
@@ -1680,7 +1681,7 @@ static inline int get_ibs_lvt_offset(void) 
{

	u64 val;



	rdmsrl(MSR_AMD64_IBSCTL, val);

	rdmsrq(MSR_AMD64_IBSCTL, val);

	if (!(val & IBSCTL_LVT_OFFSET_VALID))

		return -EINVAL;