Commit 20279628 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/dw-rockchip' 

- Check only PCIE_LINKUP, not LTSSM status, to determine whether the link
  is up (Shawn Lin)

- Increase N_FTS (used in L0s->L0 transitions) and enable ASPM L0s for Root
  Complex and Endpoint modes (Shawn Lin)

- Hide the broken ATS Capability in rockchip_pcie_ep_init() instead of
  rockchip_pcie_ep_pre_init() so it stays hidden after PERST# resets
  non-sticky registers (Shawn Lin)

- Remove unused PCIE_CLIENT_GENERAL_DEBUG definition (Hans Zhang)

- Organize register and bitfield definitions logically (Hans Zhang)

- Use rockchip_pcie_link_up() to check link up instead of open coding, and
  use GENMASK() and FIELD_GET() when possible (Hans Zhang)

- Call phy_power_off() before phy_exit() in rockchip_pcie_phy_deinit()
  (Diederik de Haas)

- Return bool (not int) for link-up check in dw_pcie_ops.link_up() and
  armada8k, dra7xx, dw-rockchip, exynos, histb, keembay, keystone, kirin,
  meson, qcom, qcom-ep, rcar_gen4, spear13xx, tegra194, uniphier, visconti
  (Hans Zhang)

- Return bool (not int) for link-up check in mobiveil_pab_ops.link_up() and
  layerscape-gen4, mobiveil (Hans Zhang)

- Simplify j721e link-up check (Hans Zhang)

- Convert pci-host-common to a library so platforms that don't need native
  host controller drivers don't need to include these helper functions
  (Manivannan Sadhasivam)

* pci/controller/dw-rockchip:
  PCI: qcom: Replace PERST# sleep time with proper macro
  PCI: dw-rockchip: Replace PERST# sleep time with proper macro
  PCI: host-common: Convert to library for host controller drivers
  PCI: cadence: Simplify J721e link status check
  PCI: mobiveil: Return bool from link up check
  PCI: dwc: Return bool from link up check
  PCI: dw-rockchip: Fix PHY function call sequence in rockchip_pcie_phy_deinit()
  PCI: dw-rockchip: Use rockchip_pcie_link_up() to check link up instead of open coding
  PCI: dw-rockchip: Reorganize register and bitfield definitions
  PCI: dw-rockchip: Remove unused PCIE_CLIENT_GENERAL_DEBUG definition
  PCI: dw-rockchip: Move rockchip_pcie_ep_hide_broken_ats_cap_rk3588() to dw_pcie_ep_ops::init()
  PCI: dw-rockchip: Enable ASPM L0s capability for both RC and EP modes
  PCI: dw-rockchip: Remove PCIE_L0S_ENTRY check from rockchip_pcie_link_up()

# Conflicts:
#	drivers/pci/controller/pcie-apple.c
#	include/linux/pci-ecam.h
parents 3f0b3629 ec49e253

drivers/pci/controller/Kconfig

+4 −4
Original line number Diff line number Diff line
@@ -3,6 +3,10 @@ 
menu "PCI controller drivers"

	depends on PCI



config PCI_HOST_COMMON

	tristate

	select PCI_ECAM



config PCI_AARDVARK

	tristate "Aardvark PCIe controller"

	depends on (ARCH_MVEBU && ARM64) || COMPILE_TEST
@@ -119,10 +123,6 @@ config PCI_FTPCI100 
	depends on OF

	default ARCH_GEMINI



config PCI_HOST_COMMON

	tristate

	select PCI_ECAM



config PCI_HOST_GENERIC

	tristate "Generic PCI host controller"

	depends on OF

drivers/pci/controller/cadence/pci-j721e.c

+1 −5
Original line number Diff line number Diff line
@@ -164,11 +164,7 @@ static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie) 
	u32 reg;



	reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS);

	reg &= LINK_STATUS;

	if (reg == LINK_UP_DL_COMPLETED)

		return true;



	return false;

	return (reg & LINK_STATUS) == LINK_UP_DL_COMPLETED;

}



static const struct cdns_pcie_ops j721e_pcie_ops = {

drivers/pci/controller/dwc/pci-dra7xx.c

+2 −2
Original line number Diff line number Diff line
@@ -118,12 +118,12 @@ static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr) 
	return cpu_addr & DRA7XX_CPU_TO_BUS_ADDR;

}



static int dra7xx_pcie_link_up(struct dw_pcie *pci)

static bool dra7xx_pcie_link_up(struct dw_pcie *pci)

{

	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);

	u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);



	return !!(reg & LINK_UP);

	return reg & LINK_UP;

}



static void dra7xx_pcie_stop_link(struct dw_pcie *pci)

drivers/pci/controller/dwc/pci-exynos.c

+2 −2
Original line number Diff line number Diff line
@@ -209,12 +209,12 @@ static struct pci_ops exynos_pci_ops = { 
	.write = exynos_pcie_wr_own_conf,

};



static int exynos_pcie_link_up(struct dw_pcie *pci)

static bool exynos_pcie_link_up(struct dw_pcie *pci)

{

	struct exynos_pcie *ep = to_exynos_pcie(pci);

	u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP);



	return (val & PCIE_ELBI_XMLH_LINKUP);

	return val & PCIE_ELBI_XMLH_LINKUP;

}



static int exynos_pcie_host_init(struct dw_pcie_rp *pp)

drivers/pci/controller/dwc/pci-keystone.c

+2 −3
Original line number Diff line number Diff line
@@ -492,13 +492,12 @@ static struct pci_ops ks_pcie_ops = { 
 * @pci: A pointer to the dw_pcie structure which holds the DesignWare PCIe host

 *	 controller driver information.

 */

static int ks_pcie_link_up(struct dw_pcie *pci)

static bool ks_pcie_link_up(struct dw_pcie *pci)

{

	u32 val;



	val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);

	val &= PORT_LOGIC_LTSSM_STATE_MASK;

	return (val == PORT_LOGIC_LTSSM_STATE_L0);

	return (val & PORT_LOGIC_LTSSM_STATE_MASK) == PORT_LOGIC_LTSSM_STATE_L0;

}



static void ks_pcie_stop_link(struct dw_pcie *pci)