Commit 21822b6a authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: switch to ih_enable_ring for vega10 



use vega10_ih_enable_ring to enable all the
available ring buffers for vega10/12, RAVEN
series and RENOIR APUs

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Acked-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: default avatarDennis Li <Dennis.Li@amd.com>
Reviewed-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fd95e1b1

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

+8 −87
Original line number Diff line number Diff line
@@ -261,9 +261,10 @@ static int vega10_ih_enable_ring(struct amdgpu_device *adev, 
 */

static int vega10_ih_irq_init(struct amdgpu_device *adev)

{

	struct amdgpu_ih_ring *ih;

	u32 ih_rb_cntl, ih_chicken;

	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};

	u32 ih_chicken;

	int ret;

	int i;

	u32 tmp;



	/* disable irqs */
@@ -273,24 +274,6 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) 


	adev->nbio.funcs->ih_control(adev);



	ih = &adev->irq.ih;

	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8);

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff);



	ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);

	ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);

	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,

				   !!adev->irq.msi_enabled);

	if (amdgpu_sriov_vf(adev)) {

		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {

			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");

			return -ETIMEDOUT;

		}

	} else {

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);

	}



	if ((adev->asic_type == CHIP_ARCTURUS &&

	     adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) ||

	    adev->asic_type == CHIP_RENOIR) {
@@ -305,74 +288,12 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) 
		WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);

	}



	/* set the writeback address whether it's enabled or not */

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,

		     lower_32_bits(ih->wptr_addr));

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI,

		     upper_32_bits(ih->wptr_addr) & 0xFFFF);



	/* set rptr, wptr to 0 */

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);



	WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR,

		     vega10_ih_doorbell_rptr(ih));



	ih = &adev->irq.ih1;

	if (ih->ring_size) {

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8);

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1,

			     (ih->gpu_addr >> 40) & 0xff);



		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);

		ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);

		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

					   WPTR_OVERFLOW_ENABLE, 0);

		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

					   RB_FULL_DRAIN_ENABLE, 1);

		if (amdgpu_sriov_vf(adev)) {

			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,

						ih_rb_cntl)) {

				DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");

				return -ETIMEDOUT;

			}

		} else {

			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);

		}



		/* set rptr, wptr to 0 */

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);



		WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1,

			     vega10_ih_doorbell_rptr(ih));

	}



	ih = &adev->irq.ih2;

	if (ih->ring_size) {

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8);

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2,

			     (ih->gpu_addr >> 40) & 0xff);



		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);

		ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);



		if (amdgpu_sriov_vf(adev)) {

			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,

						ih_rb_cntl)) {

				DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");

				return -ETIMEDOUT;

			}

		} else {

			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);

	for (i = 0; i < ARRAY_SIZE(ih); i++) {

		if (ih[i]->ring_size) {

			ret = vega10_ih_enable_ring(adev, ih[i]);

			if (ret)

				return ret;

		}



		/* set rptr, wptr to 0 */

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);



		WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2,

			     vega10_ih_doorbell_rptr(ih));

	}



	tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);