Commit 21d0fc95 authored by Claudiu Manoil's avatar Claudiu Manoil Committed by Jakub Kicinski
Browse files

net: enetc: Convert 16-bit register writes to 32-bit for ENETC v4 



For ENETC v4, which is integrated into more complex SoCs (compared to v1),
16‑bit register writes are blocked in the SoC interconnect on some chips.

To be fair, it is not recommended to access 32‑bit registers of this IP
using lower‑width accessors (i.e. 16‑bit), and the only exception to
this rule was introduced by me in the initial ENETC v1 driver for the
PMAR1 register, which holds the lower 16 bits of the primary MAC address
of an SI. Meanwhile, this exception has been replicated for v4 as well.

Since LS1028 (the only SoC with ENETC v1) is not affected by this issue,
the current patch fixes the 16‑bit writes to PMAR1 starting with ENETC
v4.

Fixes: 99100d0d ("net: enetc: add preliminary support for i.MX95 ENETC PF")
Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: default avatarWei Fang <wei.fang@nxp.com>
Link: https://patch.msgid.link/20260130141035.272471-4-claudiu.manoil@nxp.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 9ae13b2e

drivers/net/ethernet/freescale/enetc/enetc4_pf.c

+2 −2
Original line number Diff line number Diff line
@@ -59,10 +59,10 @@ static void enetc4_pf_set_si_primary_mac(struct enetc_hw *hw, int si, 


	if (si != 0) {

		__raw_writel(upper, hw->port + ENETC4_PSIPMAR0(si));

		__raw_writew(lower, hw->port + ENETC4_PSIPMAR1(si));

		__raw_writel(lower, hw->port + ENETC4_PSIPMAR1(si));

	} else {

		__raw_writel(upper, hw->port + ENETC4_PMAR0);

		__raw_writew(lower, hw->port + ENETC4_PMAR1);

		__raw_writel(lower, hw->port + ENETC4_PMAR1);

	}

}