Commit 9ae13b2e authored by Claudiu Manoil's avatar Claudiu Manoil Committed by Jakub Kicinski
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net: enetc: Remove CBDR cacheability AXI settings for ENETC v4 



For ENETC v4 these settings are controlled by the global ENETC
command cache attribute registers (EnCAR), from the IERB register
block.

The hardcoded CDBR cacheability settings were inherited from LS1028A,
and should be removed from the ENETC v4 driver as they conflict
with the global IERB settings.

Fixes: e3f4a0a8 ("net: enetc: add command BD ring support for i.MX95 ENETC")
Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: default avatarWei Fang <wei.fang@nxp.com>
Link: https://patch.msgid.link/20260130141035.272471-3-claudiu.manoil@nxp.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent a69c1723

drivers/net/ethernet/freescale/enetc/enetc_cbdr.c

+0 −4
Original line number Diff line number Diff line
@@ -74,10 +74,6 @@ int enetc4_setup_cbdr(struct enetc_si *si) 
	if (!user->ring)

		return -ENOMEM;



	/* set CBDR cache attributes */

	enetc_wr(hw, ENETC_SICAR2,

		 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT);



	regs.pir = hw->reg + ENETC_SICBDRPIR;

	regs.cir = hw->reg + ENETC_SICBDRCIR;

	regs.mr = hw->reg + ENETC_SICBDRMR;