Commit 21ed19d1 authored by Jerome Brunet's avatar Jerome Brunet
Browse files

clk: amlogic: get regmap with clk_regmap_init 

Add clk_regmap_init() and use it with all clock types which derive from
clk_regmap. This helps initialise clk_regmap clocks without requiring
tables to keep track of the clock using this type.

The way it is done couples clk_regmap with the controllers, which is not
ideal. This is a temporary solution to get rid of the tables. The situation
will eventually be improved.

Link: https://lore.kernel.org/r/20250623-amlogic-clk-drop-clk-regmap-tables-v4-1-ff04918211cc@baylibre.com


Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 328d4a7e

drivers/clk/meson/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ menu "Clock support for Amlogic platforms" 
config COMMON_CLK_MESON_REGMAP

	tristate

	select REGMAP

	select MFD_SYSCON



config COMMON_CLK_MESON_DUALDIV

	tristate

drivers/clk/meson/clk-cpu-dyndiv.c

+1 −0
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate, 
};



const struct clk_ops meson_clk_cpu_dyndiv_ops = {

	.init = clk_regmap_init,

	.recalc_rate = meson_clk_cpu_dyndiv_recalc_rate,

	.determine_rate = meson_clk_cpu_dyndiv_determine_rate,

	.set_rate = meson_clk_cpu_dyndiv_set_rate,

drivers/clk/meson/clk-dualdiv.c

+2 −0
Original line number Diff line number Diff line
@@ -126,6 +126,7 @@ static int meson_clk_dualdiv_set_rate(struct clk_hw *hw, unsigned long rate, 
}



const struct clk_ops meson_clk_dualdiv_ops = {

	.init		= clk_regmap_init,

	.recalc_rate	= meson_clk_dualdiv_recalc_rate,

	.determine_rate	= meson_clk_dualdiv_determine_rate,

	.set_rate	= meson_clk_dualdiv_set_rate,
@@ -133,6 +134,7 @@ const struct clk_ops meson_clk_dualdiv_ops = { 
EXPORT_SYMBOL_NS_GPL(meson_clk_dualdiv_ops, "CLK_MESON");



const struct clk_ops meson_clk_dualdiv_ro_ops = {

	.init		= clk_regmap_init,

	.recalc_rate	= meson_clk_dualdiv_recalc_rate,

};

EXPORT_SYMBOL_NS_GPL(meson_clk_dualdiv_ro_ops, "CLK_MESON");

drivers/clk/meson/clk-mpll.c

+6 −0
Original line number Diff line number Diff line
@@ -128,6 +128,11 @@ static int mpll_init(struct clk_hw *hw) 
{

	struct clk_regmap *clk = to_clk_regmap(hw);

	struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);

	int ret;



	ret = clk_regmap_init(hw);

	if (ret)

		return ret;



	if (mpll->init_count)

		regmap_multi_reg_write(clk->map, mpll->init_regs,
@@ -151,6 +156,7 @@ static int mpll_init(struct clk_hw *hw) 
}



const struct clk_ops meson_clk_mpll_ro_ops = {

	.init		= clk_regmap_init,

	.recalc_rate	= mpll_recalc_rate,

	.determine_rate	= mpll_determine_rate,

};

drivers/clk/meson/clk-phase.c

+11 −0
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ static int meson_clk_phase_set_phase(struct clk_hw *hw, int degrees) 
}



const struct clk_ops meson_clk_phase_ops = {

	.init		= clk_regmap_init,

	.get_phase	= meson_clk_phase_get_phase,

	.set_phase	= meson_clk_phase_set_phase,

};
@@ -83,6 +84,11 @@ static int meson_clk_triphase_sync(struct clk_hw *hw) 
	struct clk_regmap *clk = to_clk_regmap(hw);

	struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);

	unsigned int val;

	int ret;



	ret = clk_regmap_init(hw);

	if (ret)

		return ret;



	/* Get phase 0 and sync it to phase 1 and 2 */

	val = meson_parm_read(clk->map, &tph->ph0);
@@ -142,6 +148,11 @@ static int meson_sclk_ws_inv_sync(struct clk_hw *hw) 
	struct clk_regmap *clk = to_clk_regmap(hw);

	struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk);

	unsigned int val;

	int ret;



	ret = clk_regmap_init(hw);

	if (ret)

		return ret;



	/* Get phase and sync the inverted value to ws */

	val = meson_parm_read(clk->map, &tph->ph);