Unverified Commit 2299d735 authored by Matt Roper's avatar Matt Roper Committed by Rodrigo Vivi
Browse files

drm/xe/tuning: Use proper register offset for GAMSTLB_CTRL 



From Xe2 onward (i.e., all platforms officially supported by the Xe
driver), the GAMSTLB_CTRL register is located at offset 0x477C and
represented by the macro "GAMSTLB_CTRL" in code.  However the register
formerly resided at offset 0xCF4C on Xe1-era platforms, and we also have
macro XEHP_GAMSTLB_CTRL that represents this old offset in the
unofficial/developer-only Xe1 code.  When tuning for the register was
added for Xe3p_LPG, the old Xe1-era macro was accidentally used instead
of the proper macro for Xe2 and beyond, causing the tuning to not be
applied properly.  Use the proper definition so that the correct offset
is written to.

Bspec: 59298
Fixes: 377c89bf ("drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KB")
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Link: https://patch.msgid.link/20260410-xe3p_tuning-v1-2-e206a62ee38f@intel.com


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
(cherry picked from commit 0b1676eafdd1ba5a5436bdca0d2a25ce56699783)
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 68fdf2c9

drivers/gpu/drm/xe/xe_tuning.c

+1 −1
Original line number Diff line number Diff line
@@ -97,7 +97,7 @@ static const struct xe_rtp_entry_sr gt_tunings[] = { 
	{ XE_RTP_NAME("Tuning: Set STLB Bank Hash Mode to 4KB"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3510, XE_RTP_END_VERSION_UNDEFINED),

		       IS_INTEGRATED),

	  XE_RTP_ACTIONS(FIELD_SET(XEHP_GAMSTLB_CTRL, BANK_HASH_MODE,

	  XE_RTP_ACTIONS(FIELD_SET(GAMSTLB_CTRL, BANK_HASH_MODE,

				   BANK_HASH_4KB_MODE))

	},

};