Commit 2676dbf9 authored by Dapeng Mi's avatar Dapeng Mi Committed by Peter Zijlstra
Browse files

perf/x86/intel: Add ICL_FIXED_0_ADAPTIVE bit into INTEL_FIXED_BITS_MASK 



ICL_FIXED_0_ADAPTIVE is missed to be added into INTEL_FIXED_BITS_MASK,
add it.

With help of this new INTEL_FIXED_BITS_MASK, intel_pmu_enable_fixed() can
be optimized. The old fixed counter control bits can be unconditionally
cleared with INTEL_FIXED_BITS_MASK and then set new control bits base on
new configuration.

Signed-off-by: default avatarDapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Tested-by: default avatarYi Lai <yi1.lai@intel.com>
Link: https://lore.kernel.org/r/20250820023032.17128-7-dapeng1.mi@linux.intel.com
parent 9b3e1197

arch/x86/events/intel/core.c

+3 −7
Original line number Diff line number Diff line
@@ -2845,8 +2845,8 @@ static void intel_pmu_enable_fixed(struct perf_event *event) 
{

	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

	struct hw_perf_event *hwc = &event->hw;

	u64 mask, bits = 0;

	int idx = hwc->idx;

	u64 bits = 0;



	if (is_topdown_idx(idx)) {

		struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
@@ -2885,14 +2885,10 @@ static void intel_pmu_enable_fixed(struct perf_event *event) 


	idx -= INTEL_PMC_IDX_FIXED;

	bits = intel_fixed_bits_by_idx(idx, bits);

	mask = intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK);



	if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {

	if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip)

		bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE);

		mask |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE);

	}



	cpuc->fixed_ctrl_val &= ~mask;

	cpuc->fixed_ctrl_val &= ~intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK);

	cpuc->fixed_ctrl_val |= bits;

}

arch/x86/include/asm/perf_event.h

+5 −1
Original line number Diff line number Diff line
@@ -35,7 +35,6 @@ 
#define ARCH_PERFMON_EVENTSEL_EQ			(1ULL << 36)

#define ARCH_PERFMON_EVENTSEL_UMASK2			(0xFFULL << 40)



#define INTEL_FIXED_BITS_MASK				0xFULL

#define INTEL_FIXED_BITS_STRIDE			4

#define INTEL_FIXED_0_KERNEL				(1ULL << 0)

#define INTEL_FIXED_0_USER				(1ULL << 1)
@@ -48,6 +47,11 @@ 
#define ICL_EVENTSEL_ADAPTIVE				(1ULL << 34)

#define ICL_FIXED_0_ADAPTIVE				(1ULL << 32)



#define INTEL_FIXED_BITS_MASK					\

	(INTEL_FIXED_0_KERNEL | INTEL_FIXED_0_USER |		\

	 INTEL_FIXED_0_ANYTHREAD | INTEL_FIXED_0_ENABLE_PMI |	\

	 ICL_FIXED_0_ADAPTIVE)



#define intel_fixed_bits_by_idx(_idx, _bits)			\

	((_bits) << ((_idx) * INTEL_FIXED_BITS_STRIDE))

arch/x86/kvm/pmu.h

+1 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
#define MSR_IA32_MISC_ENABLE_PMU_RO_MASK (MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |	\

					  MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)



/* retrieve the 4 bits for EN and PMI out of IA32_FIXED_CTR_CTRL */

/* retrieve a fixed counter bits out of IA32_FIXED_CTR_CTRL */

#define fixed_ctrl_field(ctrl_reg, idx) \

	(((ctrl_reg) >> ((idx) * INTEL_FIXED_BITS_STRIDE)) & INTEL_FIXED_BITS_MASK)