Commit 9b3e1197 authored by Dapeng Mi's avatar Dapeng Mi Committed by Peter Zijlstra
Browse files

perf/x86/intel: Change macro GLOBAL_CTRL_EN_PERF_METRICS to BIT_ULL(48) 



Macro GLOBAL_CTRL_EN_PERF_METRICS is defined to 48 instead of
BIT_ULL(48), it's inconsistent with other similar macros. This leads to
this macro is quite easily used wrongly since users thinks it's a
bit-mask just like other similar macros.

Thus change GLOBAL_CTRL_EN_PERF_METRICS to BIT_ULL(48) and eliminate
this potential misuse.

Signed-off-by: default avatarDapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Tested-by: default avatarYi Lai <yi1.lai@intel.com>
Link: https://lore.kernel.org/r/20250820023032.17128-6-dapeng1.mi@linux.intel.com
parent 0c5caea7

arch/x86/events/intel/core.c

+4 −4
Original line number Diff line number Diff line
@@ -5319,9 +5319,9 @@ static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu) 
						0, x86_pmu_num_counters(&pmu->pmu), 0, 0);



	if (pmu->intel_cap.perf_metrics)

		pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;

		pmu->intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS;

	else

		pmu->intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);

		pmu->intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS;



	intel_pmu_check_event_constraints(pmu->event_constraints,

					  pmu->cntr_mask64,
@@ -5456,7 +5456,7 @@ static void intel_pmu_cpu_starting(int cpu) 
		rdmsrq(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);

		if (!perf_cap.perf_metrics) {

			x86_pmu.intel_cap.perf_metrics = 0;

			x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);

			x86_pmu.intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS;

		}

	}
@@ -7790,7 +7790,7 @@ __init int intel_pmu_init(void) 
	}



	if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics)

		x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;

		x86_pmu.intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS;



	if (x86_pmu.intel_cap.pebs_timing_info)

		x86_pmu.flags |= PMU_FL_RETIRE_LATENCY;

arch/x86/include/asm/perf_event.h

+1 −1
Original line number Diff line number Diff line
@@ -430,7 +430,7 @@ static inline bool is_topdown_idx(int idx) 
#define GLOBAL_STATUS_TRACE_TOPAPMI		BIT_ULL(GLOBAL_STATUS_TRACE_TOPAPMI_BIT)

#define GLOBAL_STATUS_PERF_METRICS_OVF_BIT	48



#define GLOBAL_CTRL_EN_PERF_METRICS		48

#define GLOBAL_CTRL_EN_PERF_METRICS		BIT_ULL(48)

/*

 * We model guest LBR event tracing as another fixed-mode PMC like BTS.

 *