Commit 267f2c56 authored by J. Neuschäfer's avatar J. Neuschäfer Committed by Bartosz Golaszewski
Browse files

dt-bindings: gpio: fairchild,74hc595: Document chip select vs. latch clock 

From looking at the data sheets, it is not obvious that CS# and latch
clock can be treated at the same, but doing so works fine and saves the
hassle of (1) trying to specify a SPI device without CS, and (2) adding
another property to drive the latch clock[1].

[1]: https://lore.kernel.org/lkml/20241213-gpio74-v1-2-fa2c089caf41@posteo.net/



Signed-off-by: default avatarJ. Neuschäfer <j.ne@posteo.net>
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241224-gpio74-v2-3-bbcf14183191@posteo.net


Signed-off-by: default avatarBartosz Golaszewski <bartosz.golaszewski@linaro.org>
parent c9ec045f

Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml

+17 −0
Original line number Diff line number Diff line
@@ -6,6 +6,23 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 


title: Generic 8-bit shift register



description: |

  NOTE: These chips nominally don't have a chip select pin. They do however

  have a rising-edge triggered latch clock (or storage register clock) pin,

  which behaves like an active-low chip select.



  After the bits are shifted into the shift register, CS# is driven high, which

  the 74HC595 sees as a rising edge on the latch clock that results in a

  transfer of the bits from the shift register to the storage register and thus

  to the output pins.

                      _   _       _   _

  shift clock    ____| |_| |_..._| |_| |_________



  latch clock                           * trigger

                 ___                     ________

  chip select#      |___________________|





maintainers:

  - Maxime Ripard <mripard@kernel.org>