Commit 28a12ef3 authored by Andreas Schwab's avatar Andreas Schwab Committed by Paul Walmsley
Browse files

errata/sifive: remove unreliable warn_miss_errata 



When both the SiFive and MIPS errata are enabled then
sifive_errata_patch_func emits a wrong and misleading warning claiming
that the SiFive errata haven't been applied.  This happens because
sifive_errata_patch_func is being called twice, once for the kernel image
and once for the vdso image.  The vdso image has alternative entries
for the MIPS errata, but none for the SiFive errata.

Signed-off-by: default avatarAndreas Schwab <schwab@suse.de>
Link: https://patch.msgid.link/mvmv7i8q8gg.fsf@suse.de


Signed-off-by: default avatarPaul Walmsley <pjw@kernel.org>
parent 494d4a05

arch/riscv/errata/sifive/errata.c

+0 −18
Original line number Diff line number Diff line
@@ -75,26 +75,12 @@ static u32 __init_or_module sifive_errata_probe(unsigned long archid, 
	return cpu_req_errata;

}



static void __init_or_module warn_miss_errata(u32 miss_errata)

{

	int i;



	pr_warn("----------------------------------------------------------------\n");

	pr_warn("WARNING: Missing the following errata may cause potential issues\n");

	for (i = 0; i < ERRATA_SIFIVE_NUMBER; i++)

		if (miss_errata & 0x1 << i)

			pr_warn("\tSiFive Errata[%d]:%s\n", i, errata_list[i].name);

	pr_warn("Please enable the corresponding Kconfig to apply them\n");

	pr_warn("----------------------------------------------------------------\n");

}



void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,

			      unsigned long archid, unsigned long impid,

			      unsigned int stage)

{

	struct alt_entry *alt;

	u32 cpu_req_errata;

	u32 cpu_apply_errata = 0;

	u32 tmp;



	BUILD_BUG_ON(ERRATA_SIFIVE_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE);
@@ -118,10 +104,6 @@ void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, 
			patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt),

					  alt->alt_len);

			mutex_unlock(&text_mutex);

			cpu_apply_errata |= tmp;

		}

	}

	if (stage != RISCV_ALTERNATIVES_MODULE &&

	    cpu_apply_errata != cpu_req_errata)

		warn_miss_errata(cpu_req_errata - cpu_apply_errata);

}