Commit 2a294fa2 authored by Miquel Raynal's avatar Miquel Raynal
Browse files

mtd: spinand: Use more specific naming for the read ID op 



SPI operations have been initially described through macros implicitly
implying the use of a single SPI SDR bus. Macros for supporting dual and
quad I/O transfers have been added on top, generally inspired by vendor
naming, followed by DTR operations. Soon we might see octal
and even octal DTR operations as well (including the opcode byte).

Let's clarify what the macro really means by describing the expected bus
topology in the read ID macro name.

Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
parent d54e34c5

drivers/mtd/nand/spi/core.c

+1 −1
Original line number Diff line number Diff line
@@ -583,7 +583,7 @@ int spinand_wait(struct spinand_device *spinand, unsigned long initial_delay_us, 
static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr,

			      u8 ndummy, u8 *buf)

{

	struct spi_mem_op op = SPINAND_READID_OP(

	struct spi_mem_op op = SPINAND_READID_1S_1S_1S_OP(

		naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN);

	int ret;

include/linux/mtd/spinand.h

+1 −1
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ 
		   SPI_MEM_OP_NO_DUMMY,					\

		   SPI_MEM_OP_NO_DATA)



#define SPINAND_READID_OP(naddr, ndummy, buf, len)			\

#define SPINAND_READID_1S_1S_1S_OP(naddr, ndummy, buf, len)		\

	SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1),				\

		   SPI_MEM_OP_ADDR(naddr, 0, 1),			\

		   SPI_MEM_OP_DUMMY(ndummy, 1),				\