Commit 2d09a944 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull arm64 updates from Catalin Marinas:
 "Nothing major this time around.

  Apart from the usual perf/PMU updates, some page table cleanups, the
  notable features are average CPU frequency based on the AMUv1
  counters, CONFIG_HOTPLUG_SMT and MOPS instructions (memcpy/memset) in
  the uaccess routines.

  Perf and PMUs:

   - Support for the 'Rainier' CPU PMU from Arm

   - Preparatory driver changes and cleanups that pave the way for BRBE
     support

   - Support for partial virtualisation of the Apple-M1 PMU

   - Support for the second event filter in Arm CSPMU designs

   - Minor fixes and cleanups (CMN and DWC PMUs)

   - Enable EL2 requirements for FEAT_PMUv3p9

  Power, CPU topology:

   - Support for AMUv1-based average CPU frequency

   - Run-time SMT control wired up for arm64 (CONFIG_HOTPLUG_SMT). It
     adds a generic topology_is_primary_thread() function overridden by
     x86 and powerpc

  New(ish) features:

   - MOPS (memcpy/memset) support for the uaccess routines

  Security/confidential compute:

   - Fix the DMA address for devices used in Realms with Arm CCA. The
     CCA architecture uses the address bit to differentiate between
     shared and private addresses

   - Spectre-BHB: assume CPUs Linux doesn't know about vulnerable by
     default

  Memory management clean-ups:

   - Drop the P*D_TABLE_BIT definition in preparation for 128-bit PTEs

   - Some minor page table accessor clean-ups

   - PIE/POE (permission indirection/overlay) helpers clean-up

  Kselftests:

   - MTE: skip hugetlb tests if MTE is not supported on such mappings
     and user correct naming for sync/async tag checking modes

  Miscellaneous:

   - Add a PKEY_UNRESTRICTED definition as 0 to uapi (toolchain people
     request)

   - Sysreg updates for new register fields

   - CPU type info for some Qualcomm Kryo cores"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (72 commits)
  arm64: mm: Don't use %pK through printk
  perf/arm_cspmu: Fix missing io.h include
  arm64: errata: Add newer ARM cores to the spectre_bhb_loop_affected() lists
  arm64: cputype: Add MIDR_CORTEX_A76AE
  arm64: errata: Add KRYO 2XX/3XX/4XX silver cores to Spectre BHB safe list
  arm64: errata: Assume that unknown CPUs _are_ vulnerable to Spectre BHB
  arm64: errata: Add QCOM_KRYO_4XX_GOLD to the spectre_bhb_k24_list
  arm64/sysreg: Enforce whole word match for open/close tokens
  arm64/sysreg: Fix unbalanced closing block
  arm64: Kconfig: Enable HOTPLUG_SMT
  arm64: topology: Support SMT control on ACPI based system
  arch_topology: Support SMT control for OF based system
  cpu/SMT: Provide a default topology_is_primary_thread()
  arm64/mm: Define PTDESC_ORDER
  perf/arm_cspmu: Add PMEVFILT2R support
  perf/arm_cspmu: Generalise event filtering
  perf/arm_cspmu: Move register definitons to header
  arm64/kernel: Always use level 2 or higher for early mappings
  arm64/mm: Drop PXD_TABLE_BIT
  arm64/mm: Check pmd_table() in pmd_trans_huge()
  ...
parents 317a76a9 64fa6b93
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+16 −1
Original line number Diff line number Diff line
@@ -248,6 +248,20 @@ are the following:
	If that frequency cannot be determined, this attribute should not
	be present.

``cpuinfo_avg_freq``
        An average frequency (in KHz) of all CPUs belonging to a given policy,
        derived from a hardware provided feedback and reported on a time frame
        spanning at most few milliseconds.

        This is expected to be based on the frequency the hardware actually runs
        at and, as such, might require specialised hardware support (such as AMU
        extension on ARM). If one cannot be determined, this attribute should
        not be present.

        Note, that failed attempt to retrieve current frequency for a given
        CPU(s) will result in an appropriate error, i.e: EAGAIN for CPU that
        remains idle (raised on ARM).

``cpuinfo_max_freq``
	Maximum possible operating frequency the CPUs belonging to this policy
	can run at (in kHz).
@@ -293,7 +307,8 @@ are the following:
	Some architectures (e.g. ``x86``) may attempt to provide information
	more precisely reflecting the current CPU frequency through this
	attribute, but that still may not be the exact current CPU frequency as
	seen by the hardware at the moment.
	seen by the hardware at the moment. This behavior though, is only
	available via c:macro:``CPUFREQ_ARCH_CUR_FREQ`` option.

``scaling_driver``
	The scaling driver currently in use.
+22 −0
Original line number Diff line number Diff line
@@ -288,6 +288,12 @@ Before jumping into the kernel, the following conditions must be met:

    - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.

  For CPUs with the Fine Grained Traps 2 (FEAT_FGT2) extension present:

  - If EL3 is present and the kernel is entered at EL2:

    - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1.

  For CPUs with support for HCRX_EL2 (FEAT_HCX) present:

  - If EL3 is present and the kernel is entered at EL2:
@@ -382,6 +388,22 @@ Before jumping into the kernel, the following conditions must be met:

    - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.

  For CPUs with the Performance Monitors Extension (FEAT_PMUv3p9):

 - If EL3 is present:

    - MDCR_EL3.EnPM2 (bit 7) must be initialised to 0b1.

 - If the kernel is entered at EL1 and EL2 is present:

    - HDFGRTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
    - HDFGRTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
    - HDFGRTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.

    - HDFGWTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
    - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
    - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.

  For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS):

  - If the kernel is entered at EL1 and EL2 is present:
+2 −1
Original line number Diff line number Diff line
@@ -251,6 +251,7 @@ config ARM64
	select HAVE_KRETPROBES
	select HAVE_GENERIC_VDSO
	select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
	select HOTPLUG_SMT if HOTPLUG_CPU
	select IRQ_DOMAIN
	select IRQ_FORCED_THREADING
	select KASAN_VMALLOC if KASAN
@@ -324,7 +325,7 @@ config ARCH_MMAP_RND_BITS_MIN
	default 18

# max bits determined by the following formula:
#  VA_BITS - PAGE_SHIFT - 3
#  VA_BITS - PTDESC_TABLE_SHIFT
config ARCH_MMAP_RND_BITS_MAX
	default 19 if ARM64_VA_BITS=36
	default 24 if ARM64_VA_BITS=39
+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@
#define PMCR0_PMI_ENABLE_8_9	GENMASK(45, 44)

#define SYS_IMP_APL_PMCR1_EL1	sys_reg(3, 1, 15, 1, 0)
#define SYS_IMP_APL_PMCR1_EL12	sys_reg(3, 1, 15, 7, 2)
#define PMCR1_COUNT_A64_EL0_0_7	GENMASK(15, 8)
#define PMCR1_COUNT_A64_EL1_0_7	GENMASK(23, 16)
#define PMCR1_COUNT_A64_EL0_8_9	GENMASK(41, 40)
+9 −1
Original line number Diff line number Diff line
@@ -9,7 +9,8 @@
#define EX_TYPE_BPF			1
#define EX_TYPE_UACCESS_ERR_ZERO	2
#define EX_TYPE_KACCESS_ERR_ZERO	3
#define EX_TYPE_LOAD_UNALIGNED_ZEROPAD	4
#define EX_TYPE_UACCESS_CPY		4
#define EX_TYPE_LOAD_UNALIGNED_ZEROPAD	5

/* Data fields for EX_TYPE_UACCESS_ERR_ZERO */
#define EX_DATA_REG_ERR_SHIFT	0
@@ -23,6 +24,9 @@
#define EX_DATA_REG_ADDR_SHIFT	5
#define EX_DATA_REG_ADDR	GENMASK(9, 5)

/* Data fields for EX_TYPE_UACCESS_CPY */
#define EX_DATA_UACCESS_WRITE	BIT(0)

#ifdef __ASSEMBLY__

#define __ASM_EXTABLE_RAW(insn, fixup, type, data)	\
@@ -69,6 +73,10 @@
	.endif
	.endm

	.macro		_asm_extable_uaccess_cpy, insn, fixup, uaccess_is_write
	__ASM_EXTABLE_RAW(\insn, \fixup, EX_TYPE_UACCESS_CPY, \uaccess_is_write)
	.endm

#else /* __ASSEMBLY__ */

#include <linux/stringify.h>
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