Commit 2e0f2394 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch kvm-arm64/nv-at-pan into kvmarm-master/next 



* kvm-arm64/nv-at-pan:
  : .
  : Add NV support for the AT family of instructions, which mostly results
  : in adding a page table walker that deals with most of the complexity
  : of the architecture.
  :
  : From the cover letter:
  :
  : "Another task that a hypervisor supporting NV on arm64 has to deal with
  : is to emulate the AT instruction, because we multiplex all the S1
  : translations on a single set of registers, and the guest S2 is never
  : truly resident on the CPU.
  :
  : So given that we lie about page tables, we also have to lie about
  : translation instructions, hence the emulation. Things are made
  : complicated by the fact that guest S1 page tables can be swapped out,
  : and that our shadow S2 is likely to be incomplete. So while using AT
  : to emulate AT is tempting (and useful), it is not going to always
  : work, and we thus need a fallback in the shape of a SW S1 walker."
  : .
  KVM: arm64: nv: Add support for FEAT_ATS1A
  KVM: arm64: nv: Plumb handling of AT S1* traps from EL2
  KVM: arm64: nv: Make AT+PAN instructions aware of FEAT_PAN3
  KVM: arm64: nv: Sanitise SCTLR_EL1.EPAN according to VM configuration
  KVM: arm64: nv: Add SW walker for AT S1 emulation
  KVM: arm64: nv: Make ps_to_output_size() generally available
  KVM: arm64: nv: Add emulation of AT S12E{0,1}{R,W}
  KVM: arm64: nv: Add basic emulation of AT S1E2{R,W}
  KVM: arm64: nv: Add basic emulation of AT S1E1{R,W}P
  KVM: arm64: nv: Add basic emulation of AT S1E{0,1}{R,W}
  KVM: arm64: nv: Honor absence of FEAT_PAN2
  KVM: arm64: nv: Turn upper_attr for S2 walk into the full descriptor
  KVM: arm64: nv: Enforce S2 alignment when contiguous bit is set
  arm64: Add ESR_ELx_FSC_ADDRSZ_L() helper
  arm64: Add system register encoding for PSTATE.PAN
  arm64: Add PAR_EL1 field description
  arm64: Add missing APTable and TCR_ELx.HPD masks
  KVM: arm64: Make kvm_at() take an OP_AT_*

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>

# Conflicts:
#	arch/arm64/kvm/nested.c
parents f77e63e2 ff987ffc

arch/arm64/include/asm/esr.h

+3 −2
Original line number Diff line number Diff line
@@ -122,8 +122,8 @@ 
#define ESR_ELx_FSC_SECC_TTW(n)	(0x1c + (n))



/* Status codes for individual page table levels */

#define ESR_ELx_FSC_ACCESS_L(n)	(ESR_ELx_FSC_ACCESS + n)

#define ESR_ELx_FSC_PERM_L(n)	(ESR_ELx_FSC_PERM + n)

#define ESR_ELx_FSC_ACCESS_L(n)	(ESR_ELx_FSC_ACCESS + (n))

#define ESR_ELx_FSC_PERM_L(n)	(ESR_ELx_FSC_PERM + (n))



#define ESR_ELx_FSC_FAULT_nL	(0x2C)

#define ESR_ELx_FSC_FAULT_L(n)	(((n) < 0 ? ESR_ELx_FSC_FAULT_nL : \
@@ -161,6 +161,7 @@ 


/* ISS field definitions for exceptions taken in to Hyp */

#define ESR_ELx_FSC_ADDRSZ	(0x00)

#define ESR_ELx_FSC_ADDRSZ_L(n)	(ESR_ELx_FSC_ADDRSZ + (n))

#define ESR_ELx_CV		(UL(1) << 24)

#define ESR_ELx_COND_SHIFT	(20)

#define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)

arch/arm64/include/asm/kvm_arm.h

+1 −0
Original line number Diff line number Diff line
@@ -107,6 +107,7 @@ 
/* TCR_EL2 Registers bits */

#define TCR_EL2_DS		(1UL << 32)

#define TCR_EL2_RES1		((1U << 31) | (1 << 23))

#define TCR_EL2_HPD		(1 << 24)

#define TCR_EL2_TBI		(1 << 20)

#define TCR_EL2_PS_SHIFT	16

#define TCR_EL2_PS_MASK		(7 << TCR_EL2_PS_SHIFT)

arch/arm64/include/asm/kvm_asm.h

+5 −1
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
#include <asm/hyp_image.h>

#include <asm/insn.h>

#include <asm/virt.h>

#include <asm/sysreg.h>



#define ARM_EXIT_WITH_SERROR_BIT  31

#define ARM_EXCEPTION_CODE(x)	  ((x) & ~(1U << ARM_EXIT_WITH_SERROR_BIT))
@@ -235,6 +236,9 @@ extern void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu); 
extern int __kvm_tlbi_s1e2(struct kvm_s2_mmu *mmu, u64 va, u64 sys_encoding);



extern void __kvm_timer_set_cntvoff(u64 cntvoff);

extern void __kvm_at_s1e01(struct kvm_vcpu *vcpu, u32 op, u64 vaddr);

extern void __kvm_at_s1e2(struct kvm_vcpu *vcpu, u32 op, u64 vaddr);

extern void __kvm_at_s12(struct kvm_vcpu *vcpu, u32 op, u64 vaddr);



extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
@@ -259,7 +263,7 @@ extern u64 __kvm_get_mdcr_el2(void); 
	asm volatile(							\

	"	mrs	%1, spsr_el2\n"					\

	"	mrs	%2, elr_el2\n"					\

	"1:	at	"at_op", %3\n"					\

	"1:	" __msr_s(at_op, "%3") "\n"				\

	"	isb\n"							\

	"	b	9f\n"						\

	"2:	msr	spsr_el2, %1\n"					\

arch/arm64/include/asm/kvm_nested.h

+38 −2
Original line number Diff line number Diff line
@@ -85,7 +85,7 @@ struct kvm_s2_trans { 
	bool readable;

	int level;

	u32 esr;

	u64 upper_attr;

	u64 desc;

};



static inline phys_addr_t kvm_s2_trans_output(struct kvm_s2_trans *trans)
@@ -115,7 +115,7 @@ static inline bool kvm_s2_trans_writable(struct kvm_s2_trans *trans) 


static inline bool kvm_s2_trans_executable(struct kvm_s2_trans *trans)

{

	return !(trans->upper_attr & BIT(54));

	return !(trans->desc & BIT(54));

}



extern int kvm_walk_nested_s2(struct kvm_vcpu *vcpu, phys_addr_t gipa,
@@ -205,4 +205,40 @@ static inline u64 kvm_encode_nested_level(struct kvm_s2_trans *trans) 
	return FIELD_PREP(KVM_NV_GUEST_MAP_SZ, trans->level);

}



/* Adjust alignment for the contiguous bit as per StageOA() */

#define contiguous_bit_shift(d, wi, l)					\

	({								\

		u8 shift = 0;						\

									\

		if ((d) & PTE_CONT) {					\

			switch (BIT((wi)->pgshift)) {			\

			case SZ_4K:					\

				shift = 4;				\

				break;					\

			case SZ_16K:					\

				shift = (l) == 2 ? 5 : 7;		\

				break;					\

			case SZ_64K:					\

				shift = 5;				\

				break;					\

			}						\

		}							\

									\

		shift;							\

	})



static inline unsigned int ps_to_output_size(unsigned int ps)

{

	switch (ps) {

	case 0: return 32;

	case 1: return 36;

	case 2: return 40;

	case 3: return 42;

	case 4: return 44;

	case 5:

	default:

		return 48;

	}

}



#endif /* __ARM64_KVM_NESTED_H */

arch/arm64/include/asm/pgtable-hwdef.h

+9 −0
Original line number Diff line number Diff line
@@ -204,6 +204,11 @@ 
 */

#define PTE_S2_MEMATTR(t)	(_AT(pteval_t, (t)) << 2)



/*

 * Hierarchical permission for Stage-1 tables

 */

#define S1_TABLE_AP		(_AT(pmdval_t, 3) << 61)



/*

 * Highest possible physical address supported.

 */
@@ -298,6 +303,10 @@ 
#define TCR_TBI1		(UL(1) << 38)

#define TCR_HA			(UL(1) << 39)

#define TCR_HD			(UL(1) << 40)

#define TCR_HPD0_SHIFT		41

#define TCR_HPD0		(UL(1) << TCR_HPD0_SHIFT)

#define TCR_HPD1_SHIFT		42

#define TCR_HPD1		(UL(1) << TCR_HPD1_SHIFT)

#define TCR_TBID0		(UL(1) << 51)

#define TCR_TBID1		(UL(1) << 52)

#define TCR_NFD0		(UL(1) << 53)