Unverified Commit 2f2cd9f3 authored by Alexandre Ghiti's avatar Alexandre Ghiti
Browse files

Merge patch series "riscv: Add bfloat16 instruction support" 

Inochi Amaoto <inochiama@gmail.com> says:

Add description for the BFloat16 precision Floating-Point ISA extension,
(Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62
("Added Chapter title to BF16") of the riscv-isa-manual.

* patches from https://lore.kernel.org/r/20250213003849.147358-1-inochiama@gmail.com

:
  riscv: hwprobe: export bfloat16 ISA extension
  riscv: add ISA extension parsing for bfloat16 ISA extension
  dt-bindings: riscv: add bfloat16 ISA extension description

Signed-off-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20250213003849.147358-1-inochiama@gmail.com
parents d9708b19 a4863e00

Documentation/arch/riscv/hwprobe.rst

+12 −0
Original line number Diff line number Diff line
@@ -248,6 +248,18 @@ The following keys are defined: 
  * :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as

       defined in version 1.0 of the RISC-V Pointer Masking extensions.



  * :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as

       defined in the RISC-V ISA manual starting from commit 4dc23d6229de

       ("Added Chapter title to BF16").



  * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as

       defined in the RISC-V ISA manual starting from commit 4dc23d6229de

       ("Added Chapter title to BF16").



  * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as

       defined in the RISC-V ISA manual starting from commit 4dc23d6229de

       ("Added Chapter title to BF16").



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to

     :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was

     mistakenly classified as a bitmask rather than a value.

Documentation/devicetree/bindings/riscv/extensions.yaml

+45 −0
Original line number Diff line number Diff line
@@ -329,6 +329,12 @@ properties: 
            instructions, as ratified in commit 056b6ff ("Zfa is ratified") of

            riscv-isa-manual.



        - const: zfbfmin

          description:

            The standard Zfbfmin extension which provides minimal support for

            16-bit half-precision brain floating-point instructions, as ratified

            in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.



        - const: zfh

          description:

            The standard Zfh extension for 16-bit half-precision binary
@@ -525,6 +531,18 @@ properties: 
            in commit 6f702a2 ("Vector extensions are now ratified") of

            riscv-v-spec.



        - const: zvfbfmin

          description:

            The standard Zvfbfmin extension for minimal support for vectored

            16-bit half-precision brain floating-point instructions, as ratified

            in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.



        - const: zvfbfwma

          description:

            The standard Zvfbfwma extension for vectored half-precision brain

            floating-point widening multiply-accumulate instructions, as ratified

            in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.



        - const: zvfh

          description:

            The standard Zvfh extension for vectored half-precision
@@ -673,6 +691,33 @@ properties: 
        then:

          contains:

            const: zca

      # Zfbfmin depends on F

      - if:

          contains:

            const: zfbfmin

        then:

          contains:

            const: f

      # Zvfbfmin depends on V or Zve32f

      - if:

          contains:

            const: zvfbfmin

        then:

          oneOf:

            - contains:

                const: v

            - contains:

                const: zve32f

      # Zvfbfwma depends on Zfbfmin and Zvfbfmin

      - if:

          contains:

            const: zvfbfwma

        then:

          allOf:

            - contains:

                const: zfbfmin

            - contains:

                const: zvfbfmin



allOf:

  # Zcf extension does not exist on rv64

arch/riscv/include/asm/hwcap.h

+3 −0
Original line number Diff line number Diff line
@@ -100,6 +100,9 @@ 
#define RISCV_ISA_EXT_ZICCRSE		91

#define RISCV_ISA_EXT_SVADE		92

#define RISCV_ISA_EXT_SVADU		93

#define RISCV_ISA_EXT_ZFBFMIN		94

#define RISCV_ISA_EXT_ZVFBFMIN		95

#define RISCV_ISA_EXT_ZVFBFWMA		96



#define RISCV_ISA_EXT_XLINUXENVCFG	127

arch/riscv/include/uapi/asm/hwprobe.h

+3 −0
Original line number Diff line number Diff line
@@ -75,6 +75,9 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_EXT_SUPM		(1ULL << 49)

#define		RISCV_HWPROBE_EXT_ZICNTR	(1ULL << 50)

#define		RISCV_HWPROBE_EXT_ZIHPM		(1ULL << 51)

#define		RISCV_HWPROBE_EXT_ZFBFMIN	(1ULL << 52)

#define		RISCV_HWPROBE_EXT_ZVFBFMIN	(1ULL << 53)

#define		RISCV_HWPROBE_EXT_ZVFBFWMA	(1ULL << 54)

#define RISCV_HWPROBE_KEY_CPUPERF_0	5

#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)

#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)

arch/riscv/kernel/cpufeature.c

+35 −0
Original line number Diff line number Diff line
@@ -80,6 +80,15 @@ bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned i 
}

EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);



static int riscv_ext_f_depends(const struct riscv_isa_ext_data *data,

			       const unsigned long *isa_bitmap)

{

	if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f))

		return 0;



	return -EPROBE_DEFER;

}



static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data,

				     const unsigned long *isa_bitmap)

{
@@ -140,6 +149,28 @@ static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data, 
	return -EPROBE_DEFER;

}



static int riscv_vector_f_validate(const struct riscv_isa_ext_data *data,

				   const unsigned long *isa_bitmap)

{

	if (!IS_ENABLED(CONFIG_RISCV_ISA_V))

		return -EINVAL;



	if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVE32F))

		return 0;



	return -EPROBE_DEFER;

}



static int riscv_ext_zvfbfwma_validate(const struct riscv_isa_ext_data *data,

				       const unsigned long *isa_bitmap)

{

	if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZFBFMIN) &&

	    __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVFBFMIN))

		return 0;



	return -EPROBE_DEFER;

}



static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data,

				    const unsigned long *isa_bitmap)

{
@@ -345,6 +376,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { 
	__RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),

	__RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS),

	__RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),

	__RISCV_ISA_EXT_DATA_VALIDATE(zfbfmin, RISCV_ISA_EXT_ZFBFMIN, riscv_ext_f_depends),

	__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),

	__RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),

	__RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
@@ -377,6 +409,9 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { 
	__RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),

	__RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),

	__RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),

	__RISCV_ISA_EXT_DATA_VALIDATE(zvfbfmin, RISCV_ISA_EXT_ZVFBFMIN, riscv_vector_f_validate),

	__RISCV_ISA_EXT_DATA_VALIDATE(zvfbfwma, RISCV_ISA_EXT_ZVFBFWMA,

				      riscv_ext_zvfbfwma_validate),

	__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),

	__RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),

	__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),