Unverified Commit 30eb2e6e authored by Miquel Raynal's avatar Miquel Raynal Committed by Mark Brown
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spi: zynqmp-gqspi: Support per spi-mem operation frequency switches 



Every ->exec_op() call correctly configures the spi bus speed to the
maximum allowed frequency for the memory using the constant spi default
parameter. Since we can now have per-operation constraints, let's use
the value that comes from the spi-mem operation structure instead. In
case there is no specific limitation for this operation, the default spi
device value will be given anyway.

The per-operation frequency capability is thus advertised to the spi-mem
core.

Cc: Michal Simek <michal.simek@amd.com>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://patch.msgid.link/20241224-winbond-6-11-rc1-quad-support-v2-17-ad218dbc406f@bootlin.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 9a68f6c8

drivers/spi/spi-zynqmp-gqspi.c

+9 −4
Original line number Diff line number Diff line
@@ -535,7 +535,7 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi, 
 * zynqmp_qspi_config_op - Configure QSPI controller for specified

 *				transfer

 * @xqspi:	Pointer to the zynqmp_qspi structure

 * @qspi:	Pointer to the spi_device structure

 * @op:		The memory operation to execute

 *

 * Sets the operational mode of QSPI controller for the next QSPI transfer and

 * sets the requested clock frequency.
@@ -553,12 +553,12 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi, 
 *	frequency supported by controller.

 */

static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi,

				 struct spi_device *qspi)

				 const struct spi_mem_op *op)

{

	ulong clk_rate;

	u32 config_reg, req_speed_hz, baud_rate_val = 0;



	req_speed_hz = qspi->max_speed_hz;

	req_speed_hz = op->max_freq;



	if (xqspi->speed_hz != req_speed_hz) {

		xqspi->speed_hz = req_speed_hz;
@@ -1072,7 +1072,7 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem, 
		op->dummy.buswidth, op->data.buswidth);



	mutex_lock(&xqspi->op_lock);

	zynqmp_qspi_config_op(xqspi, mem->spi);

	zynqmp_qspi_config_op(xqspi, op);

	zynqmp_qspi_chipselect(mem->spi, false);

	genfifoentry |= xqspi->genfifocs;

	genfifoentry |= xqspi->genfifobus;
@@ -1224,6 +1224,10 @@ static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = { 
	.exec_op = zynqmp_qspi_exec_op,

};



static const struct spi_controller_mem_caps zynqmp_qspi_mem_caps = {

	.per_op_freq = true,

};



/**

 * zynqmp_qspi_probe - Probe method for the QSPI driver

 * @pdev:	Pointer to the platform_device structure
@@ -1333,6 +1337,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) 


	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);

	ctlr->mem_ops = &zynqmp_qspi_mem_ops;

	ctlr->mem_caps = &zynqmp_qspi_mem_caps;

	ctlr->setup = zynqmp_qspi_setup_op;

	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);

	ctlr->dev.of_node = np;