Commit 3323532a authored by Ian Rogers's avatar Ian Rogers Committed by Namhyung Kim
Browse files

perf vendor events: Update meteorlake events and add counter information 

Update events from v1.08 to v1.10.

Bring in the event updates v1.10:
https://github.com/intel/perfmon/commit/3bee3dc150164df0bec5980ca5586930730e5778
v1.09:
https://github.com/intel/perfmon/commit/01c8c99f17a72460b2eaf7efe3495913f36c9d42

Add counter information. The most recent RFC patch set using this
information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/

New events are:
EXE_ACTIVITY.2_3_PORTS_UTIL,
FP_INST_RETIRED.128B_DP,
FP_INST_RETIRED.128B_SP,
FP_INST_RETIRED.256B_DP,
FP_INST_RETIRED.32B_SP,
FP_INST_RETIRED.64B_DP,
FP_VINT_UOPS_EXECUTED.STD,
L2_LINES_OUT.USELESS_HWPF,
L2_RQSTS.SWPF_HIT,
L2_RQSTS.SWPF_MISS,
LOAD_HIT_PREFETCH.SWPF,
MACHINE_CLEARS.ANY,
MACHINE_CLEARS.MRN_NUKE,
MISC_RETIRED.LBR_INSERTS,
SW_PREFETCH_ACCESS.ANY.

The metrics aren't updated as they require retirement latency support
that is added in this series:
https://lore.kernel.org/lkml/20240613033631.199800-1-weilin.wang@intel.com/



Co-authored-by: default avatarWeilin Wang <weilin.wang@intel.com>
Co-authored-by: default avatarCaleb Biggers <caleb.biggers@intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-24-irogers@google.com
parent 82eff6ee

tools/perf/pmu-events/arch/x86/mapfile.csv

+1 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ GenuineIntel-6-3E,v24,ivytown,core 
GenuineIntel-6-2D,v24,jaketown,core

GenuineIntel-6-(57|85),v16,knightslanding,core

GenuineIntel-6-BD,v1.01,lunarlake,core

GenuineIntel-6-A[AC],v1.08,meteorlake,core

GenuineIntel-6-A[AC],v1.10,meteorlake,core

GenuineIntel-6-1[AEF],v4,nehalemep,core

GenuineIntel-6-2E,v4,nehalemex,core

GenuineIntel-6-A7,v1.02,rocketlake,core

tools/perf/pmu-events/arch/x86/meteorlake/cache.json

+166 −57

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/meteorlake/floating-point.json

+80 −6
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.",

        "Counter": "0,1,2,3,4,5,6,7",

        "CounterMask": "1",

        "EventCode": "0xcd",

        "EventName": "ARITH.FPDIV_ACTIVE",
@@ -10,6 +11,7 @@ 
    },

    {

        "BriefDescription": "This event counts the cycles the floating point divider is busy.",

        "Counter": "0,1,2,3,4,5,6,7",

        "CounterMask": "1",

        "EventCode": "0xb0",

        "EventName": "ARITH.FPDIV_ACTIVE",
@@ -19,6 +21,7 @@ 
    },

    {

        "BriefDescription": "Counts all microcode FP assists.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc1",

        "EventName": "ASSISTS.FP",

        "PublicDescription": "Counts all microcode Floating Point assists.",
@@ -28,6 +31,7 @@ 
    },

    {

        "BriefDescription": "ASSISTS.SSE_AVX_MIX",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc1",

        "EventName": "ASSISTS.SSE_AVX_MIX",

        "SampleAfterValue": "1000003",
@@ -36,6 +40,7 @@ 
    },

    {

        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xb3",

        "EventName": "FP_ARITH_DISPATCHED.PORT_0",

        "SampleAfterValue": "2000003",
@@ -44,6 +49,7 @@ 
    },

    {

        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xb3",

        "EventName": "FP_ARITH_DISPATCHED.PORT_1",

        "SampleAfterValue": "2000003",
@@ -52,6 +58,7 @@ 
    },

    {

        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xb3",

        "EventName": "FP_ARITH_DISPATCHED.PORT_5",

        "SampleAfterValue": "2000003",
@@ -60,6 +67,7 @@ 
    },

    {

        "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xb3",

        "EventName": "FP_ARITH_DISPATCHED.V0",

        "SampleAfterValue": "2000003",
@@ -68,6 +76,7 @@ 
    },

    {

        "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xb3",

        "EventName": "FP_ARITH_DISPATCHED.V1",

        "SampleAfterValue": "2000003",
@@ -76,6 +85,7 @@ 
    },

    {

        "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xb3",

        "EventName": "FP_ARITH_DISPATCHED.V2",

        "SampleAfterValue": "2000003",
@@ -84,6 +94,7 @@ 
    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",

        "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -93,6 +104,7 @@ 
    },

    {

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",

        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -102,6 +114,7 @@ 
    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",

        "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -111,6 +124,7 @@ 
    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",

        "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -120,6 +134,7 @@ 
    },

    {

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",

        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -129,6 +144,7 @@ 
    },

    {

        "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below.  Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR",

        "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -138,6 +154,7 @@ 
    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",

        "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -147,6 +164,7 @@ 
    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",

        "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -156,6 +174,7 @@ 
    },

    {

        "BriefDescription": "Number of any Vector retired FP arithmetic instructions",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.VECTOR",

        "PublicDescription": "Number of any Vector retired FP arithmetic instructions.  The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -165,53 +184,108 @@ 
    },

    {

        "BriefDescription": "Counts the number of all types of floating point operations per uop with all default weighting",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc8",

        "EventName": "FP_FLOPS_RETIRED.ALL",

        "PEBS": "1",

        "SampleAfterValue": "1000003",

        "UMask": "0x3",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP64]",

        "Counter": "0,1,2,3,4,5,6,7",

        "Deprecated": "1",

        "EventCode": "0xc8",

        "EventName": "FP_FLOPS_RETIRED.DP",

        "PEBS": "1",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of floating point operations that produce 32 bit single precision results [This event is alias to FP_FLOPS_RETIRED.SP]",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc8",

        "EventName": "FP_FLOPS_RETIRED.FP32",

        "PEBS": "1",

        "SampleAfterValue": "1000003",

        "UMask": "0x2",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of floating point operations that produce 64 bit double precision results [This event is alias to FP_FLOPS_RETIRED.DP]",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc8",

        "EventName": "FP_FLOPS_RETIRED.FP64",

        "PEBS": "1",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP32]",

        "Counter": "0,1,2,3,4,5,6,7",

        "Deprecated": "1",

        "EventCode": "0xc8",

        "EventName": "FP_FLOPS_RETIRED.SP",

        "PEBS": "1",

        "SampleAfterValue": "1000003",

        "UMask": "0x2",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the total number of  floating point retired instructions.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_INST_RETIRED.128B_DP",

        "SampleAfterValue": "1000003",

        "UMask": "0x8",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_INST_RETIRED.128B_SP",

        "SampleAfterValue": "1000003",

        "UMask": "0x4",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_INST_RETIRED.256B_DP",

        "SampleAfterValue": "1000003",

        "UMask": "0x20",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_INST_RETIRED.32B_SP",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_INST_RETIRED.64B_DP",

        "SampleAfterValue": "1000003",

        "UMask": "0x2",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of uops executed on floating point and vector integer store data port.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xb2",

        "EventName": "FP_VINT_UOPS_EXECUTED.STD",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc3",

        "EventName": "MACHINE_CLEARS.FP_ASSIST",

        "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
@@ -221,9 +295,9 @@ 
    },

    {

        "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc2",

        "EventName": "UOPS_RETIRED.FPDIV",

        "PEBS": "1",

        "SampleAfterValue": "2000003",

        "UMask": "0x8",

        "Unit": "cpu_atom"

tools/perf/pmu-events/arch/x86/meteorlake/frontend.json

+49 −20

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/meteorlake/memory.json

+34 −28

File changed.

Preview size limit exceeded, changes collapsed.