Commit 82eff6ee authored by Ian Rogers's avatar Ian Rogers Committed by Namhyung Kim
Browse files

perf vendor events: Add lunarlake counter information 

Add counter information necessary for optimizing event grouping the
perf tool.

The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/

The information was added in:
https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4765e1


and later patches.

Co-authored-by: default avatarWeilin Wang <weilin.wang@intel.com>
Co-authored-by: default avatarCaleb Biggers <caleb.biggers@intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-23-irogers@google.com
parent 025cce25

tools/perf/pmu-events/arch/x86/lunarlake/cache.json

+20 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts the number of L2 Cache Accesses Counts the total number of L2 Cache Accesses - sum of hits, misses, rejects  front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only, per core event",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x24",

        "EventName": "L2_REQUEST.ALL",

        "PublicDescription": "Counts the number of L2 Cache Accesses Counts the total number of L2 Cache Accesses - sum of hits, misses, rejects  front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only.",
@@ -10,6 +11,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.MISS",

        "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
@@ -19,6 +21,7 @@ 
    },

    {

        "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",

        "Counter": "0,1,2,3,4,5,6,7,8,9",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.MISS",

        "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
@@ -28,6 +31,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.REFERENCE",

        "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
@@ -37,6 +41,7 @@ 
    },

    {

        "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",

        "Counter": "0,1,2,3,4,5,6,7,8,9",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.REFERENCE",

        "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
@@ -46,6 +51,7 @@ 
    },

    {

        "BriefDescription": "Retired load instructions.",

        "Counter": "0,1,2,3",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_INST_RETIRED.ALL_LOADS",
@@ -57,6 +63,7 @@ 
    },

    {

        "BriefDescription": "Retired store instructions.",

        "Counter": "0,1,2,3",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_INST_RETIRED.ALL_STORES",
@@ -68,6 +75,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of load uops retired.",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
@@ -78,6 +86,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of store uops retired.",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
@@ -88,6 +97,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024",
@@ -100,6 +110,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
@@ -112,6 +123,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
@@ -124,6 +136,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048",
@@ -136,6 +149,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
@@ -148,6 +162,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
@@ -160,6 +175,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
@@ -172,6 +188,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
@@ -184,6 +201,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
@@ -196,6 +214,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
@@ -208,6 +227,7 @@ 
    },

    {

        "BriefDescription": "Counts the number of  stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",

        "Counter": "0,1,2,3,4,5,6,7",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",

tools/perf/pmu-events/arch/x86/lunarlake/frontend.json

+3 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x80",

        "EventName": "ICACHE.ACCESSES",

        "SampleAfterValue": "200003",
@@ -9,6 +10,7 @@ 
    },

    {

        "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0x80",

        "EventName": "ICACHE.MISSES",

        "SampleAfterValue": "200003",
@@ -17,6 +19,7 @@ 
    },

    {

        "BriefDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.",

        "Counter": "0,1,2,3,4,5,6,7,8,9",

        "EventCode": "0x9c",

        "EventName": "IDQ_BUBBLES.CORE",

        "PublicDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.",

tools/perf/pmu-events/arch/x86/lunarlake/memory.json

+15 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",

        "Counter": "0,1,2,3,4,5,6,7,8,9",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024",
@@ -14,6 +15,7 @@ 
    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",

        "Counter": "0,1,2,3,4,5,6,7,8,9",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
@@ -27,6 +29,7 @@ 
    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",

        "Counter": "0,1,2,3,4,5,6,7,8,9",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
@@ -40,6 +43,7 @@ 
    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.",

        "Counter": "0,1,2,3,4,5,6,7,8,9",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048",
@@ -53,6 +57,7 @@ 
    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",

        "Counter": "0,1,2,3,4,5,6,7,8,9",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
@@ -66,6 +71,7 @@ 
    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",

        "Counter": "0,1,2,3,4,5,6,7,8,9",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
@@ -79,6 +85,7 @@ 
    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",

        "Counter": "0,1,2,3,4,5,6,7,8,9",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
@@ -92,6 +99,7 @@ 
    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",

        "Counter": "0,1,2,3,4,5,6,7,8,9",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
@@ -105,6 +113,7 @@ 
    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",

        "Counter": "0,1,2,3,4,5,6,7,8,9",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
@@ -118,6 +127,7 @@ 
    },

    {

        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",

        "Counter": "0,1,2,3,4,5,6,7,8,9",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
@@ -131,6 +141,7 @@ 
    },

    {

        "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",

        "Counter": "0,1",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
@@ -142,6 +153,7 @@ 
    },

    {

        "BriefDescription": "Counts cacheable demand data reads were not supplied by the L3 cache.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",
@@ -152,6 +164,7 @@ 
    },

    {

        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",
@@ -162,6 +175,7 @@ 
    },

    {

        "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO were not supplied by the L3 cache.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",
@@ -172,6 +186,7 @@ 
    },

    {

        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_RFO.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

tools/perf/pmu-events/arch/x86/lunarlake/other.json

+6 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts cacheable demand data reads Catch all value for any response types - this includes response types not define in the OCR.  If this is set all other response types will be ignored",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",
@@ -11,6 +12,7 @@ 
    },

    {

        "BriefDescription": "Counts demand data reads that have any type of response.",

        "Counter": "0,1,2,3",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",
@@ -21,6 +23,7 @@ 
    },

    {

        "BriefDescription": "Counts cacheable demand data reads were supplied by DRAM.",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -31,6 +34,7 @@ 
    },

    {

        "BriefDescription": "Counts demand data reads that were supplied by DRAM.",

        "Counter": "0,1,2,3",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_DATA_RD.DRAM",

        "MSRIndex": "0x1a6,0x1a7",
@@ -41,6 +45,7 @@ 
    },

    {

        "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO Catch all value for any response types - this includes response types not define in the OCR.  If this is set all other response types will be ignored",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",
@@ -51,6 +56,7 @@ 
    },

    {

        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",

        "Counter": "0,1,2,3",

        "EventCode": "0x2A,0x2B",

        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json

+36 −0

File changed.

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