Unverified Commit 3359866b authored by Clément Léger's avatar Clément Léger Committed by Palmer Dabbelt
Browse files

riscv: hwprobe: export Zicond extension 



Export the zicond extension to userspace using hwprobe.

Signed-off-by: default avatarClément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/20231220155723.684081-7-cleger@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 154a3706

Documentation/arch/riscv/hwprobe.rst

+5 −0
Original line number Diff line number Diff line
@@ -169,6 +169,11 @@ The following keys are defined: 
       defined in the Atomic Compare-and-Swap (CAS) instructions manual starting

       from commit 5059e0ca641c ("update to ratified").



  * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as

       defined in the RISC-V Integer Conditional (Zicond) operations extension

       manual starting from commit 95cf1f9 ("Add changes requested by Ved

       during signoff")



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

arch/riscv/include/uapi/asm/hwprobe.h

+1 −0
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@@ -58,6 +58,7 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_EXT_ZFA		(1ULL << 32)

#define		RISCV_HWPROBE_EXT_ZTSO		(1ULL << 33)

#define		RISCV_HWPROBE_EXT_ZACAS		(1ULL << 34)

#define		RISCV_HWPROBE_EXT_ZICOND	(1ULL << 35)

#define RISCV_HWPROBE_KEY_CPUPERF_0	5

#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)

#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)

arch/riscv/kernel/sys_riscv.c

+1 −0
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@@ -176,6 +176,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, 
		EXT_KEY(ZIHINTNTL);

		EXT_KEY(ZTSO);

		EXT_KEY(ZACAS);

		EXT_KEY(ZICOND);



		if (has_vector()) {

			EXT_KEY(ZVBB);