Commit 35db1da4 authored by Matthew Auld's avatar Matthew Auld Committed by Lucas De Marchi
Browse files

drm/xe: move DPT l2 flush to a more sensible place 



Only need the flush for DPT host updates here. Normal GGTT updates don't
need special flush.

Fixes: 01570b44 ("drm/xe/bmg: implement Wa_16023588340")
Signed-off-by: default avatarMatthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: stable@vger.kernel.org # v6.12+
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20250606104546.1996818-4-matthew.auld@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent 0dd2dd01

drivers/gpu/drm/xe/display/xe_fb_pin.c

+3 −2
Original line number Diff line number Diff line
@@ -163,6 +163,9 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb, 


	vma->dpt = dpt;

	vma->node = dpt->ggtt_node[tile0->id];



	/* Ensure DPT writes are flushed */

	xe_device_l2_flush(xe);

	return 0;

}
@@ -326,8 +329,6 @@ static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb, 
	if (ret)

		goto err_unpin;



	/* Ensure DPT writes are flushed */

	xe_device_l2_flush(xe);

	return vma;



err_unpin: