Commit 383ca7be authored by Vasily Khoruzhick's avatar Vasily Khoruzhick Committed by Chen-Yu Tsai
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clk: sunxi-ng: a64: stop force-selecting PLL-MIPI as TCON0 parent 



Stop force-selecting PLL-MIPI as TCON0 parent, since it breaks video
output on Pinebook that uses RGB to eDP bridge.

Partially revert commit ca1170b6 ("clk: sunxi-ng: a64: force
select PLL_MIPI in TCON0 mux"), while still leaving
CLK_SET_RATE_NO_REPARENT flag set, since we do not want the clock to
be reparented.

The issue is that apparently different TCON0 outputs require a different
clock, or the mux might be selecting the output type.

I did an experiment: I manually configured PLL_MIPI and PLL_VIDEO0_2X
to the same clock rate and flipped the switch with devmem. Experiment
clearly showed that whenever PLL_MIPI is selected as TCON0 clock parent,
the video output stops working.

Therefore, TCON0 clock parent corresponding to the output type must be
assigned in the device tree.

Fixes: ca1170b6 ("clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux")
Reviewed-by: default avatarDragan Simic <dsimic@manjaro.org>
Reviewed-by: default avatarChen-Yu Tsai <wens@csie.org>
Tested-by: Frank Oltmanns <frank@oltmanns.dev> # on PinePhone
Tested-by: Stuart Gathman <stuart@gathman.org> # on OG Pinebook
Signed-off-by: default avatarVasily Khoruzhick <anarsoul@gmail.com>
Link: https://patch.msgid.link/20250104074035.1611136-5-anarsoul@gmail.com


Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
parent 0f368cb7

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

+4 −9
Original line number Diff line number Diff line
@@ -535,11 +535,11 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 
				 CLK_SET_RATE_PARENT);



/*

 * DSI output seems to work only when PLL_MIPI selected. Set it and prevent

 * the mux from reparenting.

 * Experiments showed that RGB output requires pll-video0-2x, while DSI

 * requires pll-mipi. It will not work with incorrect clock, the screen will

 * be blank.

 * sun50i-a64.dtsi assigns pll-mipi as TCON0 parent by default

 */

#define SUN50I_A64_TCON0_CLK_REG	0x118



static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };

static const u8 tcon0_table[] = { 0, 2, };

static SUNXI_CCU_MUX_TABLE_WITH_GATE_CLOSEST(tcon0_clk, "tcon0", tcon0_parents,
@@ -959,11 +959,6 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev) 


	writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);



	/* Set PLL MIPI as parent for TCON0 */

	val = readl(reg + SUN50I_A64_TCON0_CLK_REG);

	val &= ~GENMASK(26, 24);

	writel(val | (0 << 24), reg + SUN50I_A64_TCON0_CLK_REG);



	ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);

	if (ret)

		return ret;