Unverified Commit 38e8c418 authored by Riana Tauro's avatar Riana Tauro Committed by Rodrigo Vivi
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drm/xe: Enable Coarse Power Gating 



Enable power gating for all units and sub-pipes that
are disabled by default.

v2: change the init function name
    use symmetric calls for enable/disable pg
    re-pharase commit message (Rodrigo)
    modify the sub-pipe power gating condition

v3: set hysteresis value for render and media
    when GuC PC is disabled
    skip CPG for PVC (Vinay)

v4: rebase

Signed-off-by: default avatarRiana Tauro <riana.tauro@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> #v2
Reviewed-by: default avatarVinay Belgaumkar <vinay.belgaumkar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240524070916.143022-3-riana.tauro@intel.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 9276bcc2

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+4 −0
Original line number Diff line number Diff line
@@ -309,6 +309,8 @@ 
#define   RC_CTL_RC6_ENABLE			REG_BIT(18)

#define RC_STATE				XE_REG(0xa094)

#define RC_IDLE_HYSTERSIS			XE_REG(0xa0ac)

#define MEDIA_POWERGATE_IDLE_HYSTERESIS		XE_REG(0xa0c4)

#define RENDER_POWERGATE_IDLE_HYSTERESIS	XE_REG(0xa0c8)



#define PMINTRMSK				XE_REG(0xa168)

#define   PMINTR_DISABLE_REDIRECT_TO_GUC	REG_BIT(31)
@@ -317,6 +319,8 @@ 
#define FORCEWAKE_GT				XE_REG(0xa188)



#define POWERGATE_ENABLE			XE_REG(0xa210)

#define   RENDER_POWERGATE_ENABLE		REG_BIT(0)

#define   MEDIA_POWERGATE_ENABLE		REG_BIT(1)

#define   VDN_HCP_POWERGATE_ENABLE(n)		REG_BIT(3 + 2 * (n))

#define   VDN_MFXVDENC_POWERGATE_ENABLE(n)	REG_BIT(4 + 2 * (n))

drivers/gpu/drm/xe/xe_gt.c

+8 −4
Original line number Diff line number Diff line
@@ -366,10 +366,6 @@ static int gt_fw_domain_init(struct xe_gt *gt) 
			xe_lmtt_init(&gt_to_tile(gt)->sriov.pf.lmtt);

	}



	err = xe_gt_idle_sysfs_init(&gt->gtidle);

	if (err)

		goto err_force_wake;



	/* Enable per hw engine IRQs */

	xe_irq_enable_hwe(gt);
@@ -554,6 +550,10 @@ int xe_gt_init(struct xe_gt *gt) 
	if (err)

		return err;



	err = xe_gt_idle_init(&gt->gtidle);

	if (err)

		return err;



	err = xe_gt_freq_init(gt);

	if (err)

		return err;
@@ -760,6 +760,8 @@ int xe_gt_suspend(struct xe_gt *gt) 
	if (err)

		goto err_force_wake;



	xe_gt_idle_disable_pg(gt);



	XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));

	xe_gt_dbg(gt, "suspended\n");
@@ -786,6 +788,8 @@ int xe_gt_resume(struct xe_gt *gt) 
	if (err)

		goto err_force_wake;



	xe_gt_idle_enable_pg(gt);



	XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));

	xe_gt_dbg(gt, "resumed\n");

drivers/gpu/drm/xe/xe_gt_idle.c

+53 −4
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include "xe_gt_sysfs.h"

#include "xe_guc_pc.h"

#include "regs/xe_gt_regs.h"

#include "xe_macros.h"

#include "xe_mmio.h"

#include "xe_pm.h"
@@ -93,6 +94,50 @@ static u64 get_residency_ms(struct xe_gt_idle *gtidle, u64 cur_residency) 
	return cur_residency;

}



void xe_gt_idle_enable_pg(struct xe_gt *gt)

{

	struct xe_device *xe = gt_to_xe(gt);

	u32 pg_enable;

	int i, j;



	/* Disable CPG for PVC */

	if (xe->info.platform == XE_PVC)

		return;



	xe_device_assert_mem_access(gt_to_xe(gt));



	pg_enable = RENDER_POWERGATE_ENABLE | MEDIA_POWERGATE_ENABLE;



	for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {

		if ((gt->info.engine_mask & BIT(i)))

			pg_enable |= (VDN_HCP_POWERGATE_ENABLE(j) |

				      VDN_MFXVDENC_POWERGATE_ENABLE(j));

	}



	XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FW_GT));

	if (xe->info.skip_guc_pc) {

		/*

		 * GuC sets the hysteresis value when GuC PC is enabled

		 * else set it to 25 (25 * 1.28us)

		 */

		xe_mmio_write32(gt, MEDIA_POWERGATE_IDLE_HYSTERESIS, 25);

		xe_mmio_write32(gt, RENDER_POWERGATE_IDLE_HYSTERESIS, 25);

	}



	xe_mmio_write32(gt, POWERGATE_ENABLE, pg_enable);

	XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FW_GT));

}



void xe_gt_idle_disable_pg(struct xe_gt *gt)

{

	xe_device_assert_mem_access(gt_to_xe(gt));

	XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FW_GT));



	xe_mmio_write32(gt, POWERGATE_ENABLE, 0);



	XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FW_GT));

}



static ssize_t name_show(struct device *dev,

			 struct device_attribute *attr, char *buff)

{
@@ -145,15 +190,18 @@ static const struct attribute *gt_idle_attrs[] = { 
	NULL,

};



static void gt_idle_sysfs_fini(void *arg)

static void gt_idle_fini(void *arg)

{

	struct kobject *kobj = arg;

	struct xe_gt *gt = kobj_to_gt(kobj->parent);



	xe_gt_idle_disable_pg(gt);



	sysfs_remove_files(kobj, gt_idle_attrs);

	kobject_put(kobj);

}



int xe_gt_idle_sysfs_init(struct xe_gt_idle *gtidle)

int xe_gt_idle_init(struct xe_gt_idle *gtidle)

{

	struct xe_gt *gt = gtidle_to_gt(gtidle);

	struct xe_device *xe = gt_to_xe(gt);
@@ -182,7 +230,9 @@ int xe_gt_idle_sysfs_init(struct xe_gt_idle *gtidle) 
		return err;

	}



	return devm_add_action_or_reset(xe->drm.dev, gt_idle_sysfs_fini, kobj);

	xe_gt_idle_enable_pg(gt);



	return devm_add_action_or_reset(xe->drm.dev, gt_idle_fini, kobj);

}



void xe_gt_idle_enable_c6(struct xe_gt *gt)
@@ -202,7 +252,6 @@ void xe_gt_idle_disable_c6(struct xe_gt *gt) 
	xe_device_assert_mem_access(gt_to_xe(gt));

	xe_force_wake_assert_held(gt_to_fw(gt), XE_FORCEWAKE_ALL);



	xe_mmio_write32(gt, POWERGATE_ENABLE, 0);

	xe_mmio_write32(gt, RC_CONTROL, 0);

	xe_mmio_write32(gt, RC_STATE, 0);

}

drivers/gpu/drm/xe/xe_gt_idle.h

+3 −1
Original line number Diff line number Diff line
@@ -10,8 +10,10 @@ 


struct xe_gt;



int xe_gt_idle_sysfs_init(struct xe_gt_idle *gtidle);

int xe_gt_idle_init(struct xe_gt_idle *gtidle);

void xe_gt_idle_enable_c6(struct xe_gt *gt);

void xe_gt_idle_disable_c6(struct xe_gt *gt);

void xe_gt_idle_enable_pg(struct xe_gt *gt);

void xe_gt_idle_disable_pg(struct xe_gt *gt);



#endif /* _XE_GT_IDLE_H_ */